./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 07:28:46,650 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 07:28:46,651 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 07:28:46,658 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 07:28:46,658 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 07:28:46,659 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 07:28:46,660 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 07:28:46,661 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 07:28:46,662 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 07:28:46,662 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 07:28:46,663 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 07:28:46,663 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 07:28:46,664 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 07:28:46,664 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 07:28:46,665 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 07:28:46,666 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 07:28:46,667 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 07:28:46,668 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 07:28:46,670 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 07:28:46,671 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 07:28:46,672 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 07:28:46,673 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 07:28:46,674 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 07:28:46,675 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 07:28:46,675 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 07:28:46,675 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 07:28:46,676 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 07:28:46,676 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 07:28:46,677 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 07:28:46,678 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 07:28:46,678 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 07:28:46,679 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 07:28:46,679 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 07:28:46,679 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 07:28:46,680 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 07:28:46,680 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 07:28:46,680 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Default.epf [2018-11-23 07:28:46,691 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 07:28:46,691 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 07:28:46,692 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 07:28:46,692 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 07:28:46,692 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 07:28:46,692 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 07:28:46,692 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 07:28:46,692 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Log string format=TERM [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 07:28:46,693 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 07:28:46,694 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 07:28:46,694 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 07:28:46,695 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 07:28:46,695 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:28:46,696 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 07:28:46,696 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-11-23 07:28:46,697 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-11-23 07:28:46,718 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 07:28:46,727 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 07:28:46,729 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 07:28:46,730 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 07:28:46,730 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 07:28:46,730 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:28:46,766 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/0f6669aa5/9c12b0d8488d42e686f082138db3c54a/FLAG197b39697 [2018-11-23 07:28:47,227 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 07:28:47,228 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:28:47,244 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/0f6669aa5/9c12b0d8488d42e686f082138db3c54a/FLAG197b39697 [2018-11-23 07:28:47,529 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/0f6669aa5/9c12b0d8488d42e686f082138db3c54a [2018-11-23 07:28:47,531 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 07:28:47,532 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 07:28:47,532 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 07:28:47,532 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 07:28:47,535 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 07:28:47,536 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:28:47" (1/1) ... [2018-11-23 07:28:47,538 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13f1c9f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:47, skipping insertion in model container [2018-11-23 07:28:47,538 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:28:47" (1/1) ... [2018-11-23 07:28:47,547 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 07:28:47,598 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 07:28:48,155 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:28:48,169 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 07:28:48,254 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:28:48,297 INFO L195 MainTranslator]: Completed translation [2018-11-23 07:28:48,297 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48 WrapperNode [2018-11-23 07:28:48,297 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 07:28:48,298 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 07:28:48,298 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 07:28:48,298 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 07:28:48,305 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,329 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,338 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 07:28:48,339 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 07:28:48,339 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 07:28:48,339 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 07:28:48,348 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,348 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,355 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,355 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,382 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,389 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,394 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... [2018-11-23 07:28:48,400 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 07:28:48,400 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 07:28:48,400 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 07:28:48,400 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 07:28:48,402 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:28:48,445 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-11-23 07:28:48,445 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-11-23 07:28:48,445 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-11-23 07:28:48,445 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-11-23 07:28:48,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-11-23 07:28:48,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 07:28:48,446 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-23 07:28:48,446 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-11-23 07:28:48,447 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-11-23 07:28:48,447 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-11-23 07:28:48,447 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-11-23 07:28:48,447 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-11-23 07:28:48,448 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-11-23 07:28:48,448 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-11-23 07:28:48,448 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-11-23 07:28:48,448 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-11-23 07:28:48,449 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-11-23 07:28:48,449 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-11-23 07:28:48,449 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-11-23 07:28:48,449 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-11-23 07:28:48,450 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-11-23 07:28:48,450 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-23 07:28:48,450 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-11-23 07:28:48,450 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-11-23 07:28:48,450 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-11-23 07:28:48,451 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 07:28:48,451 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 07:28:48,451 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-11-23 07:28:48,451 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-11-23 07:28:48,451 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-11-23 07:28:48,451 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-11-23 07:28:48,451 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-11-23 07:28:48,451 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-11-23 07:28:48,451 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 07:28:48,452 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-11-23 07:28:48,452 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-11-23 07:28:48,452 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-11-23 07:28:48,452 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-11-23 07:28:48,453 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-11-23 07:28:48,453 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-11-23 07:28:48,453 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-11-23 07:28:48,453 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-11-23 07:28:48,453 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-11-23 07:28:48,454 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-11-23 07:28:48,454 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-11-23 07:28:48,454 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-11-23 07:28:48,454 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-11-23 07:28:48,455 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-11-23 07:28:48,455 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-11-23 07:28:48,455 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-11-23 07:28:48,455 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-11-23 07:28:48,455 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-11-23 07:28:48,455 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-11-23 07:28:48,455 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-11-23 07:28:48,455 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-11-23 07:28:48,455 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-11-23 07:28:48,456 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-11-23 07:28:48,456 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-11-23 07:28:48,456 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-11-23 07:28:48,456 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-11-23 07:28:48,457 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-11-23 07:28:48,457 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-23 07:28:48,457 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-23 07:28:48,457 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-11-23 07:28:48,457 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-11-23 07:28:48,457 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 07:28:48,457 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 07:28:49,299 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 07:28:49,299 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-11-23 07:28:49,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:28:49 BoogieIcfgContainer [2018-11-23 07:28:49,300 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 07:28:49,300 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 07:28:49,301 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 07:28:49,303 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 07:28:49,303 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 07:28:47" (1/3) ... [2018-11-23 07:28:49,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@336c028 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:28:49, skipping insertion in model container [2018-11-23 07:28:49,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:48" (2/3) ... [2018-11-23 07:28:49,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@336c028 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:28:49, skipping insertion in model container [2018-11-23 07:28:49,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:28:49" (3/3) ... [2018-11-23 07:28:49,306 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:28:49,312 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 07:28:49,319 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 07:28:49,329 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 07:28:49,354 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 07:28:49,354 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 07:28:49,354 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 07:28:49,355 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 07:28:49,355 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 07:28:49,355 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 07:28:49,355 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 07:28:49,356 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 07:28:49,377 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states. [2018-11-23 07:28:49,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 07:28:49,386 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:49,387 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:49,388 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:49,392 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:49,392 INFO L82 PathProgramCache]: Analyzing trace with hash 597331850, now seen corresponding path program 1 times [2018-11-23 07:28:49,393 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:49,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:49,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:49,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:49,433 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:49,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:49,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:49,630 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:49,630 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:28:49,634 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:49,637 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:28:49,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:28:49,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:28:49,647 INFO L87 Difference]: Start difference. First operand 361 states. Second operand 3 states. [2018-11-23 07:28:49,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:49,704 INFO L93 Difference]: Finished difference Result 610 states and 812 transitions. [2018-11-23 07:28:49,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:28:49,705 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-23 07:28:49,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:49,717 INFO L225 Difference]: With dead ends: 610 [2018-11-23 07:28:49,718 INFO L226 Difference]: Without dead ends: 247 [2018-11-23 07:28:49,723 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:28:49,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-11-23 07:28:49,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-11-23 07:28:49,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-11-23 07:28:49,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 312 transitions. [2018-11-23 07:28:49,776 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 312 transitions. Word has length 34 [2018-11-23 07:28:49,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:49,777 INFO L480 AbstractCegarLoop]: Abstraction has 247 states and 312 transitions. [2018-11-23 07:28:49,778 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:28:49,778 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 312 transitions. [2018-11-23 07:28:49,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 07:28:49,780 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:49,781 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:49,781 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:49,781 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:49,781 INFO L82 PathProgramCache]: Analyzing trace with hash -59782313, now seen corresponding path program 1 times [2018-11-23 07:28:49,781 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:49,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:49,785 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:49,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:49,785 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:49,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:49,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:49,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:49,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:28:49,904 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:49,905 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:28:49,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:28:49,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:28:49,906 INFO L87 Difference]: Start difference. First operand 247 states and 312 transitions. Second operand 5 states. [2018-11-23 07:28:50,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:50,026 INFO L93 Difference]: Finished difference Result 724 states and 933 transitions. [2018-11-23 07:28:50,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:28:50,027 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-23 07:28:50,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:50,031 INFO L225 Difference]: With dead ends: 724 [2018-11-23 07:28:50,032 INFO L226 Difference]: Without dead ends: 491 [2018-11-23 07:28:50,033 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:28:50,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2018-11-23 07:28:50,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 478. [2018-11-23 07:28:50,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-11-23 07:28:50,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 611 transitions. [2018-11-23 07:28:50,073 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 611 transitions. Word has length 47 [2018-11-23 07:28:50,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:50,073 INFO L480 AbstractCegarLoop]: Abstraction has 478 states and 611 transitions. [2018-11-23 07:28:50,073 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:28:50,073 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 611 transitions. [2018-11-23 07:28:50,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 07:28:50,075 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:50,075 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:50,076 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:50,076 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:50,076 INFO L82 PathProgramCache]: Analyzing trace with hash -1368063503, now seen corresponding path program 1 times [2018-11-23 07:28:50,076 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:50,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,079 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:50,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,079 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:50,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:50,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:50,158 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:50,158 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:28:50,159 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:50,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:28:50,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:28:50,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:28:50,159 INFO L87 Difference]: Start difference. First operand 478 states and 611 transitions. Second operand 5 states. [2018-11-23 07:28:50,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:50,232 INFO L93 Difference]: Finished difference Result 958 states and 1239 transitions. [2018-11-23 07:28:50,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:28:50,233 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-11-23 07:28:50,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:50,236 INFO L225 Difference]: With dead ends: 958 [2018-11-23 07:28:50,236 INFO L226 Difference]: Without dead ends: 494 [2018-11-23 07:28:50,238 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:28:50,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states. [2018-11-23 07:28:50,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 482. [2018-11-23 07:28:50,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 482 states. [2018-11-23 07:28:50,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 482 states and 611 transitions. [2018-11-23 07:28:50,267 INFO L78 Accepts]: Start accepts. Automaton has 482 states and 611 transitions. Word has length 48 [2018-11-23 07:28:50,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:50,267 INFO L480 AbstractCegarLoop]: Abstraction has 482 states and 611 transitions. [2018-11-23 07:28:50,267 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:28:50,267 INFO L276 IsEmpty]: Start isEmpty. Operand 482 states and 611 transitions. [2018-11-23 07:28:50,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-23 07:28:50,269 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:50,269 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:50,269 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:50,269 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:50,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1953733175, now seen corresponding path program 1 times [2018-11-23 07:28:50,270 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:50,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,272 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:50,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,272 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:50,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:50,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:50,322 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:50,323 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:28:50,323 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:50,323 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:28:50,323 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:28:50,323 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:28:50,324 INFO L87 Difference]: Start difference. First operand 482 states and 611 transitions. Second operand 3 states. [2018-11-23 07:28:50,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:50,412 INFO L93 Difference]: Finished difference Result 1141 states and 1450 transitions. [2018-11-23 07:28:50,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:28:50,412 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-23 07:28:50,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:50,416 INFO L225 Difference]: With dead ends: 1141 [2018-11-23 07:28:50,416 INFO L226 Difference]: Without dead ends: 673 [2018-11-23 07:28:50,417 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:28:50,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states. [2018-11-23 07:28:50,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 670. [2018-11-23 07:28:50,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-11-23 07:28:50,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 851 transitions. [2018-11-23 07:28:50,467 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 851 transitions. Word has length 45 [2018-11-23 07:28:50,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:50,467 INFO L480 AbstractCegarLoop]: Abstraction has 670 states and 851 transitions. [2018-11-23 07:28:50,467 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:28:50,467 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 851 transitions. [2018-11-23 07:28:50,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 07:28:50,468 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:50,469 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:50,469 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:50,469 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:50,469 INFO L82 PathProgramCache]: Analyzing trace with hash -1115579532, now seen corresponding path program 1 times [2018-11-23 07:28:50,469 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:50,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,471 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:50,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,472 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:50,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:50,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:50,550 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:50,550 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:28:50,550 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:50,551 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:28:50,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:28:50,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:28:50,551 INFO L87 Difference]: Start difference. First operand 670 states and 851 transitions. Second operand 5 states. [2018-11-23 07:28:50,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:50,610 INFO L93 Difference]: Finished difference Result 1349 states and 1729 transitions. [2018-11-23 07:28:50,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:28:50,611 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-11-23 07:28:50,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:50,613 INFO L225 Difference]: With dead ends: 1349 [2018-11-23 07:28:50,613 INFO L226 Difference]: Without dead ends: 702 [2018-11-23 07:28:50,614 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:28:50,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-11-23 07:28:50,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 678. [2018-11-23 07:28:50,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2018-11-23 07:28:50,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 853 transitions. [2018-11-23 07:28:50,640 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 853 transitions. Word has length 49 [2018-11-23 07:28:50,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:50,640 INFO L480 AbstractCegarLoop]: Abstraction has 678 states and 853 transitions. [2018-11-23 07:28:50,640 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:28:50,640 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 853 transitions. [2018-11-23 07:28:50,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 07:28:50,641 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:50,641 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:50,641 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:50,641 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:50,642 INFO L82 PathProgramCache]: Analyzing trace with hash 275984174, now seen corresponding path program 1 times [2018-11-23 07:28:50,642 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:50,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,644 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:50,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,644 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:50,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:50,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:28:50,715 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:28:50,715 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:28:50,715 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:50,715 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:28:50,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:28:50,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:28:50,716 INFO L87 Difference]: Start difference. First operand 678 states and 853 transitions. Second operand 5 states. [2018-11-23 07:28:50,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:50,770 INFO L93 Difference]: Finished difference Result 1292 states and 1641 transitions. [2018-11-23 07:28:50,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:28:50,771 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-23 07:28:50,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:50,772 INFO L225 Difference]: With dead ends: 1292 [2018-11-23 07:28:50,772 INFO L226 Difference]: Without dead ends: 637 [2018-11-23 07:28:50,774 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:28:50,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states. [2018-11-23 07:28:50,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 619. [2018-11-23 07:28:50,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 619 states. [2018-11-23 07:28:50,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 619 states to 619 states and 771 transitions. [2018-11-23 07:28:50,794 INFO L78 Accepts]: Start accepts. Automaton has 619 states and 771 transitions. Word has length 50 [2018-11-23 07:28:50,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:50,795 INFO L480 AbstractCegarLoop]: Abstraction has 619 states and 771 transitions. [2018-11-23 07:28:50,795 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:28:50,795 INFO L276 IsEmpty]: Start isEmpty. Operand 619 states and 771 transitions. [2018-11-23 07:28:50,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-23 07:28:50,796 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:50,796 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:50,796 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:50,796 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:50,796 INFO L82 PathProgramCache]: Analyzing trace with hash -627832725, now seen corresponding path program 1 times [2018-11-23 07:28:50,796 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:50,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:50,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:50,798 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:50,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:50,900 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 07:28:50,900 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:28:50,900 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 07:28:50,901 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 63 with the following transitions: [2018-11-23 07:28:50,902 INFO L202 CegarAbsIntRunner]: [17], [19], [21], [23], [26], [29], [384], [387], [389], [409], [412], [415], [418], [434], [436], [437], [555], [578], [581], [583], [616], [621], [627], [637], [642], [644], [669], [675], [676], [694], [695], [696], [697], [699], [702], [706], [737], [738], [739], [740], [741], [742], [793], [794], [795], [799], [837], [838], [847], [849], [850], [873], [874], [875] [2018-11-23 07:28:50,925 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 07:28:50,925 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 07:28:51,153 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 07:28:51,155 INFO L272 AbstractInterpreter]: Visited 15 different actions 15 times. Never merged. Never widened. Performed 879 root evaluator evaluations with a maximum evaluation depth of 3. Performed 879 inverse root evaluator evaluations with a maximum inverse evaluation depth of 3. Never found a fixpoint. Largest state had 177 variables. [2018-11-23 07:28:51,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:51,170 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 07:28:51,284 INFO L227 lantSequenceWeakener]: Weakened 13 states. On average, predicates are now at 93.91% of their original sizes. [2018-11-23 07:28:51,284 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 07:28:51,341 INFO L415 sIntCurrentIteration]: We unified 61 AI predicates to 61 [2018-11-23 07:28:51,341 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 07:28:51,342 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 07:28:51,342 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 16 [2018-11-23 07:28:51,342 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:51,343 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 07:28:51,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 07:28:51,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-23 07:28:51,343 INFO L87 Difference]: Start difference. First operand 619 states and 771 transitions. Second operand 9 states. [2018-11-23 07:28:52,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:28:52,665 INFO L93 Difference]: Finished difference Result 1486 states and 1852 transitions. [2018-11-23 07:28:52,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 07:28:52,666 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 62 [2018-11-23 07:28:52,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:28:52,668 INFO L225 Difference]: With dead ends: 1486 [2018-11-23 07:28:52,668 INFO L226 Difference]: Without dead ends: 887 [2018-11-23 07:28:52,670 INFO L631 BasicCegarLoop]: 2 DeclaredPredicates, 62 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-11-23 07:28:52,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states. [2018-11-23 07:28:52,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 823. [2018-11-23 07:28:52,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 823 states. [2018-11-23 07:28:52,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 823 states to 823 states and 1034 transitions. [2018-11-23 07:28:52,694 INFO L78 Accepts]: Start accepts. Automaton has 823 states and 1034 transitions. Word has length 62 [2018-11-23 07:28:52,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:28:52,694 INFO L480 AbstractCegarLoop]: Abstraction has 823 states and 1034 transitions. [2018-11-23 07:28:52,694 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 07:28:52,694 INFO L276 IsEmpty]: Start isEmpty. Operand 823 states and 1034 transitions. [2018-11-23 07:28:52,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-23 07:28:52,695 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:28:52,695 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:28:52,696 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:28:52,696 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:52,696 INFO L82 PathProgramCache]: Analyzing trace with hash 722594284, now seen corresponding path program 1 times [2018-11-23 07:28:52,696 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:28:52,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:52,698 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:28:52,698 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:28:52,698 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:28:52,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:28:52,787 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 07:28:52,788 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:28:52,788 INFO L192 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-11-23 07:28:52,788 INFO L200 CegarAbsIntRunner]: Running AI on error trace of length 64 with the following transitions: [2018-11-23 07:28:52,788 INFO L202 CegarAbsIntRunner]: [17], [19], [21], [23], [26], [29], [384], [387], [389], [409], [412], [415], [418], [434], [436], [437], [555], [578], [581], [583], [616], [621], [627], [637], [642], [644], [669], [673], [675], [676], [694], [695], [696], [697], [699], [702], [706], [737], [738], [739], [740], [741], [742], [793], [794], [795], [799], [837], [838], [847], [849], [850], [873], [874], [875] [2018-11-23 07:28:52,790 INFO L148 AbstractInterpreter]: Using domain PoormanAbstractDomain with backing domain CompoundDomain [CongruenceDomain, ExplicitValueDomain] [2018-11-23 07:28:52,790 INFO L101 FixpointEngine]: Starting fixpoint engine with domain PoormanAbstractDomain (maxUnwinding=3, maxParallelStates=2) [2018-11-23 07:28:52,913 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2018-11-23 07:28:52,913 INFO L272 AbstractInterpreter]: Visited 35 different actions 43 times. Merged at 3 different actions 5 times. Never widened. Performed 1328 root evaluator evaluations with a maximum evaluation depth of 4. Performed 1328 inverse root evaluator evaluations with a maximum inverse evaluation depth of 4. Found 3 fixpoints after 3 different actions. Largest state had 177 variables. [2018-11-23 07:28:52,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:28:52,918 INFO L398 sIntCurrentIteration]: Generating AbsInt predicates [2018-11-23 07:28:53,157 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 95.89% of their original sizes. [2018-11-23 07:28:53,157 INFO L413 sIntCurrentIteration]: Unifying AI predicates [2018-11-23 07:28:53,994 INFO L415 sIntCurrentIteration]: We unified 62 AI predicates to 62 [2018-11-23 07:28:53,994 INFO L424 sIntCurrentIteration]: Finished generation of AbsInt predicates [2018-11-23 07:28:53,994 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 07:28:53,994 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [9] total 33 [2018-11-23 07:28:53,995 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:28:53,995 INFO L459 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-11-23 07:28:53,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-11-23 07:28:53,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=533, Unknown=0, NotChecked=0, Total=650 [2018-11-23 07:28:53,995 INFO L87 Difference]: Start difference. First operand 823 states and 1034 transitions. Second operand 26 states. [2018-11-23 07:28:55,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 07:28:55,252 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.IllegalArgumentException: unknown symbol (const Int (Array Int Int)) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:209) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:129) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translateStore(MappedTerm2Expression.java:291) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:157) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:129) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:165) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:129) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.util.AssumptionBuilder.constructBoogieAssumeStatement(AssumptionBuilder.java:75) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.util.TermConjunctEvaluator.getCachedCodeBlock(TermConjunctEvaluator.java:273) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.util.TermConjunctEvaluator.applyPost(TermConjunctEvaluator.java:296) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.util.TermConjunctEvaluator.lambda$4(TermConjunctEvaluator.java:178) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.util.TermConjunctEvaluator.computePost(TermConjunctEvaluator.java:93) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormanCachedPostOperation.applyPost(PoormanCachedPostOperation.java:308) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.applyPost(PoormansAbstractPostOperator.java:217) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.apply(PoormansAbstractPostOperator.java:119) at de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2.domain.transformula.poorman.PoormansAbstractPostOperator.apply(PoormansAbstractPostOperator.java:1) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.lambda$17(DisjunctiveAbstractState.java:340) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.mapCollection(DisjunctiveAbstractState.java:536) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.absint.DisjunctiveAbstractState.apply(DisjunctiveAbstractState.java:340) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.AbsIntHoareTripleChecker.checkInternalTransitionWithValidState(AbsIntHoareTripleChecker.java:352) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.AbsIntHoareTripleChecker.checkInternalAbsInt(AbsIntHoareTripleChecker.java:249) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.AbsIntHoareTripleChecker.checkInternal(AbsIntHoareTripleChecker.java:181) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.CachingHoareTripleChecker.checkInternal(CachingHoareTripleChecker.java:98) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton$InternalSuccessorComputationHelper.computeSuccWithSolver(AbstractInterpolantAutomaton.java:359) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.addOtherSuccessors(DeterministicInterpolantAutomaton.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:77) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:234) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:213) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:216) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:208) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1066) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:968) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:188) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.computeAutomataDifference(BasicCegarLoop.java:699) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.refineAbstraction(BasicCegarLoop.java:628) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:472) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-11-23 07:28:55,254 INFO L168 Benchmark]: Toolchain (without parser) took 7723.67 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 446.7 MB). Free memory was 952.7 MB in the beginning and 1.1 GB in the end (delta: -155.3 MB). Peak memory consumption was 291.4 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,256 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:28:55,256 INFO L168 Benchmark]: CACSL2BoogieTranslator took 765.30 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 173.0 MB). Free memory was 952.7 MB in the beginning and 1.1 GB in the end (delta: -177.2 MB). Peak memory consumption was 56.7 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,256 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.42 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,257 INFO L168 Benchmark]: Boogie Preprocessor took 61.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,257 INFO L168 Benchmark]: RCFGBuilder took 899.69 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.0 MB). Peak memory consumption was 115.0 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,258 INFO L168 Benchmark]: TraceAbstraction took 5953.72 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 273.7 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -103.0 MB). Peak memory consumption was 170.7 MB. Max. memory is 11.5 GB. [2018-11-23 07:28:55,260 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 765.30 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 173.0 MB). Free memory was 952.7 MB in the beginning and 1.1 GB in the end (delta: -177.2 MB). Peak memory consumption was 56.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.42 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 61.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 899.69 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.0 MB). Peak memory consumption was 115.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 5953.72 ms. Allocated memory was 1.2 GB in the beginning and 1.5 GB in the end (delta: 273.7 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -103.0 MB). Peak memory consumption was 170.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: IllegalArgumentException: unknown symbol (const Int (Array Int Int)) de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: IllegalArgumentException: unknown symbol (const Int (Array Int Int)): de.uni_freiburg.informatik.ultimate.modelcheckerutils.boogie.MappedTerm2Expression.translate(MappedTerm2Expression.java:209) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-aa41828 [2018-11-23 07:28:56,683 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 07:28:56,684 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 07:28:56,691 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 07:28:56,692 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 07:28:56,692 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 07:28:56,693 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 07:28:56,695 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 07:28:56,696 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 07:28:56,696 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 07:28:56,697 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 07:28:56,697 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 07:28:56,699 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 07:28:56,699 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 07:28:56,700 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 07:28:56,700 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 07:28:56,701 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 07:28:56,703 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 07:28:56,704 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 07:28:56,705 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 07:28:56,706 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 07:28:56,707 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 07:28:56,709 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 07:28:56,709 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 07:28:56,709 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 07:28:56,710 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 07:28:56,710 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 07:28:56,711 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 07:28:56,711 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 07:28:56,712 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 07:28:56,712 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 07:28:56,713 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 07:28:56,713 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 07:28:56,713 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 07:28:56,715 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 07:28:56,715 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 07:28:56,715 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2018-11-23 07:28:56,726 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 07:28:56,726 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 07:28:56,727 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 07:28:56,727 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 07:28:56,727 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 07:28:56,727 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 07:28:56,728 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 07:28:56,728 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 07:28:56,728 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 07:28:56,728 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 07:28:56,728 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 07:28:56,728 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 07:28:56,729 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 07:28:56,730 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 07:28:56,730 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 07:28:56,730 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 07:28:56,730 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 07:28:56,730 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:28:56,730 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 07:28:56,730 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 07:28:56,731 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-11-23 07:28:56,759 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 07:28:56,767 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 07:28:56,769 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 07:28:56,770 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 07:28:56,771 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 07:28:56,771 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:28:56,807 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/6930ce25c/d9998b0e99e44ebb98a41f49a64083ff/FLAG3478cd93d [2018-11-23 07:28:57,245 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 07:28:57,245 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:28:57,260 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/6930ce25c/d9998b0e99e44ebb98a41f49a64083ff/FLAG3478cd93d [2018-11-23 07:28:57,566 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/data/6930ce25c/d9998b0e99e44ebb98a41f49a64083ff [2018-11-23 07:28:57,569 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 07:28:57,570 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 07:28:57,571 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 07:28:57,571 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 07:28:57,574 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 07:28:57,575 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:28:57" (1/1) ... [2018-11-23 07:28:57,577 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@514d3bea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:57, skipping insertion in model container [2018-11-23 07:28:57,578 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:28:57" (1/1) ... [2018-11-23 07:28:57,585 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 07:28:57,636 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 07:28:58,122 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:28:58,142 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 07:28:58,336 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:28:58,376 INFO L195 MainTranslator]: Completed translation [2018-11-23 07:28:58,377 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58 WrapperNode [2018-11-23 07:28:58,377 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 07:28:58,378 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 07:28:58,378 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 07:28:58,378 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 07:28:58,383 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,406 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,415 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 07:28:58,415 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 07:28:58,415 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 07:28:58,416 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 07:28:58,421 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,422 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,427 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,428 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,456 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,465 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,471 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... [2018-11-23 07:28:58,478 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 07:28:58,479 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 07:28:58,479 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 07:28:58,479 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 07:28:58,480 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:28:58,513 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-11-23 07:28:58,514 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1 [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE8 [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-11-23 07:28:58,514 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-11-23 07:28:58,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-11-23 07:28:58,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-23 07:28:58,515 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-11-23 07:28:58,515 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-11-23 07:28:58,515 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-11-23 07:28:58,516 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-11-23 07:28:58,516 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-11-23 07:28:58,516 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-11-23 07:28:58,516 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-11-23 07:28:58,516 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-11-23 07:28:58,516 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-11-23 07:28:58,516 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-11-23 07:28:58,516 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-11-23 07:28:58,516 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-11-23 07:28:58,517 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-11-23 07:28:58,517 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-11-23 07:28:58,517 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-11-23 07:28:58,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-11-23 07:28:58,518 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-11-23 07:28:58,518 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-11-23 07:28:58,518 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-23 07:28:58,518 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-11-23 07:28:58,518 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-11-23 07:28:58,519 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-11-23 07:28:58,519 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-11-23 07:28:58,519 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 07:28:58,519 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 07:28:58,519 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-11-23 07:28:58,519 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-11-23 07:28:58,519 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-11-23 07:28:58,519 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-11-23 07:28:58,519 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-11-23 07:28:58,519 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 07:28:58,520 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-11-23 07:28:58,520 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-11-23 07:28:58,520 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-11-23 07:28:58,520 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-11-23 07:28:58,521 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-11-23 07:28:58,521 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-11-23 07:28:58,521 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-11-23 07:28:58,521 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-11-23 07:28:58,521 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE8 [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1 [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-11-23 07:28:58,522 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-11-23 07:28:58,522 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-11-23 07:28:58,522 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-11-23 07:28:58,523 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-11-23 07:28:58,523 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1 [2018-11-23 07:28:58,523 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-11-23 07:28:58,523 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-11-23 07:28:58,523 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-11-23 07:28:58,523 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-11-23 07:28:58,523 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-11-23 07:28:58,523 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-11-23 07:28:58,523 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-11-23 07:28:58,523 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-11-23 07:28:58,524 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-11-23 07:28:58,524 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-11-23 07:28:58,524 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-11-23 07:28:58,524 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-11-23 07:28:58,524 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-11-23 07:28:58,525 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-11-23 07:28:58,525 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-23 07:28:58,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-23 07:28:58,525 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-11-23 07:28:58,525 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-11-23 07:28:58,525 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 07:28:58,525 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 07:29:01,461 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 07:29:01,461 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-11-23 07:29:01,461 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:29:01 BoogieIcfgContainer [2018-11-23 07:29:01,462 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 07:29:01,463 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 07:29:01,463 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 07:29:01,465 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 07:29:01,466 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 07:28:57" (1/3) ... [2018-11-23 07:29:01,467 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@164ea07e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:29:01, skipping insertion in model container [2018-11-23 07:29:01,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:28:58" (2/3) ... [2018-11-23 07:29:01,467 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@164ea07e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:29:01, skipping insertion in model container [2018-11-23 07:29:01,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:29:01" (3/3) ... [2018-11-23 07:29:01,470 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-23 07:29:01,476 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 07:29:01,481 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 07:29:01,491 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 07:29:01,514 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 07:29:01,514 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 07:29:01,514 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 07:29:01,515 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 07:29:01,515 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 07:29:01,516 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 07:29:01,516 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 07:29:01,516 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 07:29:01,516 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 07:29:01,533 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states. [2018-11-23 07:29:01,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-23 07:29:01,541 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:01,542 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:01,544 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:01,547 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:01,548 INFO L82 PathProgramCache]: Analyzing trace with hash 597331850, now seen corresponding path program 1 times [2018-11-23 07:29:01,552 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:01,552 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:01,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:01,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:01,715 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:01,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:01,740 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:01,744 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:01,744 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:29:01,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:29:01,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:29:01,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:01,758 INFO L87 Difference]: Start difference. First operand 361 states. Second operand 3 states. [2018-11-23 07:29:01,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:01,836 INFO L93 Difference]: Finished difference Result 610 states and 812 transitions. [2018-11-23 07:29:01,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:29:01,837 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-23 07:29:01,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:01,848 INFO L225 Difference]: With dead ends: 610 [2018-11-23 07:29:01,848 INFO L226 Difference]: Without dead ends: 247 [2018-11-23 07:29:01,852 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:01,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-11-23 07:29:01,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-11-23 07:29:01,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-11-23 07:29:01,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 312 transitions. [2018-11-23 07:29:01,903 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 312 transitions. Word has length 34 [2018-11-23 07:29:01,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:01,904 INFO L480 AbstractCegarLoop]: Abstraction has 247 states and 312 transitions. [2018-11-23 07:29:01,904 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:29:01,904 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 312 transitions. [2018-11-23 07:29:01,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-23 07:29:01,907 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:01,908 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:01,908 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:01,908 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:01,908 INFO L82 PathProgramCache]: Analyzing trace with hash -59782313, now seen corresponding path program 1 times [2018-11-23 07:29:01,909 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:01,909 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:01,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:02,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:02,044 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:02,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:02,073 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:02,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:02,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:29:02,083 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:29:02,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:29:02,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:29:02,084 INFO L87 Difference]: Start difference. First operand 247 states and 312 transitions. Second operand 5 states. [2018-11-23 07:29:02,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:02,209 INFO L93 Difference]: Finished difference Result 724 states and 933 transitions. [2018-11-23 07:29:02,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:29:02,209 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-23 07:29:02,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:02,213 INFO L225 Difference]: With dead ends: 724 [2018-11-23 07:29:02,213 INFO L226 Difference]: Without dead ends: 491 [2018-11-23 07:29:02,215 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:29:02,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2018-11-23 07:29:02,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 478. [2018-11-23 07:29:02,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-11-23 07:29:02,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 611 transitions. [2018-11-23 07:29:02,257 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 611 transitions. Word has length 47 [2018-11-23 07:29:02,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:02,257 INFO L480 AbstractCegarLoop]: Abstraction has 478 states and 611 transitions. [2018-11-23 07:29:02,257 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:29:02,257 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 611 transitions. [2018-11-23 07:29:02,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 07:29:02,260 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:02,261 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:02,261 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:02,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:02,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1368063503, now seen corresponding path program 1 times [2018-11-23 07:29:02,262 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:02,262 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:02,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:02,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:02,393 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:02,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:02,423 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:02,425 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:02,425 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:29:02,425 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:29:02,425 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:29:02,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:29:02,426 INFO L87 Difference]: Start difference. First operand 478 states and 611 transitions. Second operand 5 states. [2018-11-23 07:29:02,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:02,511 INFO L93 Difference]: Finished difference Result 958 states and 1239 transitions. [2018-11-23 07:29:02,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:29:02,511 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-11-23 07:29:02,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:02,514 INFO L225 Difference]: With dead ends: 958 [2018-11-23 07:29:02,514 INFO L226 Difference]: Without dead ends: 494 [2018-11-23 07:29:02,515 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:29:02,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states. [2018-11-23 07:29:02,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 482. [2018-11-23 07:29:02,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 482 states. [2018-11-23 07:29:02,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 482 states and 611 transitions. [2018-11-23 07:29:02,563 INFO L78 Accepts]: Start accepts. Automaton has 482 states and 611 transitions. Word has length 48 [2018-11-23 07:29:02,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:02,564 INFO L480 AbstractCegarLoop]: Abstraction has 482 states and 611 transitions. [2018-11-23 07:29:02,564 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:29:02,564 INFO L276 IsEmpty]: Start isEmpty. Operand 482 states and 611 transitions. [2018-11-23 07:29:02,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-23 07:29:02,565 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:02,565 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:02,565 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:02,567 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:02,567 INFO L82 PathProgramCache]: Analyzing trace with hash -1953733175, now seen corresponding path program 1 times [2018-11-23 07:29:02,567 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:02,567 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:02,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:02,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:02,678 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:02,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:02,686 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:02,687 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:02,688 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:29:02,688 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:29:02,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:29:02,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:02,688 INFO L87 Difference]: Start difference. First operand 482 states and 611 transitions. Second operand 3 states. [2018-11-23 07:29:02,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:02,774 INFO L93 Difference]: Finished difference Result 1141 states and 1450 transitions. [2018-11-23 07:29:02,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:29:02,774 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-23 07:29:02,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:02,777 INFO L225 Difference]: With dead ends: 1141 [2018-11-23 07:29:02,777 INFO L226 Difference]: Without dead ends: 673 [2018-11-23 07:29:02,778 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:02,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states. [2018-11-23 07:29:02,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 670. [2018-11-23 07:29:02,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-11-23 07:29:02,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 851 transitions. [2018-11-23 07:29:02,807 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 851 transitions. Word has length 45 [2018-11-23 07:29:02,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:02,808 INFO L480 AbstractCegarLoop]: Abstraction has 670 states and 851 transitions. [2018-11-23 07:29:02,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:29:02,808 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 851 transitions. [2018-11-23 07:29:02,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-23 07:29:02,809 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:02,809 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:02,809 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:02,810 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:02,811 INFO L82 PathProgramCache]: Analyzing trace with hash -1115579532, now seen corresponding path program 1 times [2018-11-23 07:29:02,811 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:02,811 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:02,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:02,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:02,928 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:02,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:02,956 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:02,957 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:02,958 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:29:02,958 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:29:02,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:29:02,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:29:02,958 INFO L87 Difference]: Start difference. First operand 670 states and 851 transitions. Second operand 5 states. [2018-11-23 07:29:03,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:03,029 INFO L93 Difference]: Finished difference Result 1349 states and 1729 transitions. [2018-11-23 07:29:03,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:29:03,030 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-11-23 07:29:03,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:03,032 INFO L225 Difference]: With dead ends: 1349 [2018-11-23 07:29:03,032 INFO L226 Difference]: Without dead ends: 702 [2018-11-23 07:29:03,033 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:29:03,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-11-23 07:29:03,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 678. [2018-11-23 07:29:03,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2018-11-23 07:29:03,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 853 transitions. [2018-11-23 07:29:03,058 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 853 transitions. Word has length 49 [2018-11-23 07:29:03,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:03,059 INFO L480 AbstractCegarLoop]: Abstraction has 678 states and 853 transitions. [2018-11-23 07:29:03,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:29:03,059 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 853 transitions. [2018-11-23 07:29:03,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 07:29:03,060 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:03,060 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:03,060 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:03,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:03,061 INFO L82 PathProgramCache]: Analyzing trace with hash 275984174, now seen corresponding path program 1 times [2018-11-23 07:29:03,061 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:03,061 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:03,078 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:03,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:03,173 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:03,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:03,207 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:03,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:03,209 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:29:03,209 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:29:03,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:29:03,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:29:03,210 INFO L87 Difference]: Start difference. First operand 678 states and 853 transitions. Second operand 5 states. [2018-11-23 07:29:03,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:03,283 INFO L93 Difference]: Finished difference Result 1292 states and 1641 transitions. [2018-11-23 07:29:03,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:29:03,284 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-23 07:29:03,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:03,286 INFO L225 Difference]: With dead ends: 1292 [2018-11-23 07:29:03,286 INFO L226 Difference]: Without dead ends: 637 [2018-11-23 07:29:03,287 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:29:03,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states. [2018-11-23 07:29:03,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 619. [2018-11-23 07:29:03,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 619 states. [2018-11-23 07:29:03,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 619 states to 619 states and 771 transitions. [2018-11-23 07:29:03,312 INFO L78 Accepts]: Start accepts. Automaton has 619 states and 771 transitions. Word has length 50 [2018-11-23 07:29:03,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:03,312 INFO L480 AbstractCegarLoop]: Abstraction has 619 states and 771 transitions. [2018-11-23 07:29:03,312 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:29:03,312 INFO L276 IsEmpty]: Start isEmpty. Operand 619 states and 771 transitions. [2018-11-23 07:29:03,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-23 07:29:03,314 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:03,314 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:03,314 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:03,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:03,314 INFO L82 PathProgramCache]: Analyzing trace with hash -627832725, now seen corresponding path program 1 times [2018-11-23 07:29:03,315 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:03,315 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:03,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:03,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:03,432 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:03,507 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 07:29:03,507 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:03,686 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-23 07:29:03,688 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 07:29:03,688 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [9] total 13 [2018-11-23 07:29:03,689 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 07:29:03,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 07:29:03,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-11-23 07:29:03,689 INFO L87 Difference]: Start difference. First operand 619 states and 771 transitions. Second operand 13 states. [2018-11-23 07:29:06,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:06,577 INFO L93 Difference]: Finished difference Result 1683 states and 2171 transitions. [2018-11-23 07:29:06,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 07:29:06,578 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 62 [2018-11-23 07:29:06,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:06,583 INFO L225 Difference]: With dead ends: 1683 [2018-11-23 07:29:06,583 INFO L226 Difference]: Without dead ends: 1087 [2018-11-23 07:29:06,585 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 112 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=152, Invalid=498, Unknown=0, NotChecked=0, Total=650 [2018-11-23 07:29:06,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1087 states. [2018-11-23 07:29:06,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1087 to 878. [2018-11-23 07:29:06,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 878 states. [2018-11-23 07:29:06,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 878 states to 878 states and 1098 transitions. [2018-11-23 07:29:06,635 INFO L78 Accepts]: Start accepts. Automaton has 878 states and 1098 transitions. Word has length 62 [2018-11-23 07:29:06,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:06,635 INFO L480 AbstractCegarLoop]: Abstraction has 878 states and 1098 transitions. [2018-11-23 07:29:06,635 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 07:29:06,635 INFO L276 IsEmpty]: Start isEmpty. Operand 878 states and 1098 transitions. [2018-11-23 07:29:06,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-23 07:29:06,637 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:06,637 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:06,637 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:06,637 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:06,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1769783724, now seen corresponding path program 1 times [2018-11-23 07:29:06,638 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:06,639 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:06,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:06,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:06,798 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:06,858 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:06,858 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:06,976 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:06,978 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:29:06,978 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 07:29:06,989 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:07,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:07,046 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:07,053 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:07,053 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:07,172 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:07,190 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 07:29:07,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-23 07:29:07,191 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 07:29:07,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 07:29:07,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-23 07:29:07,191 INFO L87 Difference]: Start difference. First operand 878 states and 1098 transitions. Second operand 14 states. [2018-11-23 07:29:08,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:08,612 INFO L93 Difference]: Finished difference Result 2040 states and 2561 transitions. [2018-11-23 07:29:08,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 07:29:08,613 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-11-23 07:29:08,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:08,617 INFO L225 Difference]: With dead ends: 2040 [2018-11-23 07:29:08,617 INFO L226 Difference]: Without dead ends: 1185 [2018-11-23 07:29:08,619 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-11-23 07:29:08,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1185 states. [2018-11-23 07:29:08,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1185 to 1116. [2018-11-23 07:29:08,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1116 states. [2018-11-23 07:29:08,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1116 states to 1116 states and 1408 transitions. [2018-11-23 07:29:08,672 INFO L78 Accepts]: Start accepts. Automaton has 1116 states and 1408 transitions. Word has length 63 [2018-11-23 07:29:08,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:08,672 INFO L480 AbstractCegarLoop]: Abstraction has 1116 states and 1408 transitions. [2018-11-23 07:29:08,672 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 07:29:08,673 INFO L276 IsEmpty]: Start isEmpty. Operand 1116 states and 1408 transitions. [2018-11-23 07:29:08,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 07:29:08,674 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:08,674 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:08,674 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:08,674 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:08,674 INFO L82 PathProgramCache]: Analyzing trace with hash 825280740, now seen corresponding path program 1 times [2018-11-23 07:29:08,675 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:08,675 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:08,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:08,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:08,815 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:08,982 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:08,983 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:09,216 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:09,218 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:29:09,218 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 07:29:09,229 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:09,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:09,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:09,319 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:09,319 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:09,442 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:09,457 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 07:29:09,457 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-23 07:29:09,458 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 07:29:09,458 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 07:29:09,458 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-23 07:29:09,458 INFO L87 Difference]: Start difference. First operand 1116 states and 1408 transitions. Second operand 14 states. [2018-11-23 07:29:10,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:10,684 INFO L93 Difference]: Finished difference Result 2516 states and 3185 transitions. [2018-11-23 07:29:10,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 07:29:10,685 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 64 [2018-11-23 07:29:10,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:10,690 INFO L225 Difference]: With dead ends: 2516 [2018-11-23 07:29:10,690 INFO L226 Difference]: Without dead ends: 1423 [2018-11-23 07:29:10,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 241 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-11-23 07:29:10,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1423 states. [2018-11-23 07:29:10,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1423 to 1116. [2018-11-23 07:29:10,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1116 states. [2018-11-23 07:29:10,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1116 states to 1116 states and 1408 transitions. [2018-11-23 07:29:10,750 INFO L78 Accepts]: Start accepts. Automaton has 1116 states and 1408 transitions. Word has length 64 [2018-11-23 07:29:10,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:10,750 INFO L480 AbstractCegarLoop]: Abstraction has 1116 states and 1408 transitions. [2018-11-23 07:29:10,750 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 07:29:10,750 INFO L276 IsEmpty]: Start isEmpty. Operand 1116 states and 1408 transitions. [2018-11-23 07:29:10,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-23 07:29:10,752 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:10,752 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:10,752 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:10,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:10,752 INFO L82 PathProgramCache]: Analyzing trace with hash -645709563, now seen corresponding path program 1 times [2018-11-23 07:29:10,753 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:10,753 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:10,775 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:10,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:10,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:11,011 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:11,011 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:11,176 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:11,178 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:29:11,178 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 07:29:11,188 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:11,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:11,245 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:11,251 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:11,251 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:11,353 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:11,368 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 07:29:11,369 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10] total 14 [2018-11-23 07:29:11,369 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 07:29:11,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 07:29:11,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-23 07:29:11,369 INFO L87 Difference]: Start difference. First operand 1116 states and 1408 transitions. Second operand 14 states. [2018-11-23 07:29:12,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:12,678 INFO L93 Difference]: Finished difference Result 2188 states and 2756 transitions. [2018-11-23 07:29:12,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 07:29:12,678 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 65 [2018-11-23 07:29:12,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:12,683 INFO L225 Difference]: With dead ends: 2188 [2018-11-23 07:29:12,683 INFO L226 Difference]: Without dead ends: 1095 [2018-11-23 07:29:12,685 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 245 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2018-11-23 07:29:12,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1095 states. [2018-11-23 07:29:12,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1095 to 316. [2018-11-23 07:29:12,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 316 states. [2018-11-23 07:29:12,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 379 transitions. [2018-11-23 07:29:12,721 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 379 transitions. Word has length 65 [2018-11-23 07:29:12,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:12,721 INFO L480 AbstractCegarLoop]: Abstraction has 316 states and 379 transitions. [2018-11-23 07:29:12,722 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 07:29:12,722 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 379 transitions. [2018-11-23 07:29:12,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-23 07:29:12,723 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:12,723 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:12,723 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:12,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:12,723 INFO L82 PathProgramCache]: Analyzing trace with hash -1038493382, now seen corresponding path program 1 times [2018-11-23 07:29:12,724 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:12,724 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:12,745 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:12,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:12,847 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:12,856 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:29:12,857 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:12,858 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:12,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:29:12,858 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:29:12,859 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:29:12,859 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:12,859 INFO L87 Difference]: Start difference. First operand 316 states and 379 transitions. Second operand 3 states. [2018-11-23 07:29:12,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:12,952 INFO L93 Difference]: Finished difference Result 686 states and 838 transitions. [2018-11-23 07:29:12,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:29:12,953 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2018-11-23 07:29:12,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:12,954 INFO L225 Difference]: With dead ends: 686 [2018-11-23 07:29:12,954 INFO L226 Difference]: Without dead ends: 393 [2018-11-23 07:29:12,955 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:12,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2018-11-23 07:29:12,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2018-11-23 07:29:12,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 393 states. [2018-11-23 07:29:12,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 475 transitions. [2018-11-23 07:29:12,978 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 475 transitions. Word has length 69 [2018-11-23 07:29:12,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:12,978 INFO L480 AbstractCegarLoop]: Abstraction has 393 states and 475 transitions. [2018-11-23 07:29:12,978 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:29:12,979 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 475 transitions. [2018-11-23 07:29:12,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-11-23 07:29:12,980 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:12,980 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:12,980 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:12,980 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:12,980 INFO L82 PathProgramCache]: Analyzing trace with hash -1067644734, now seen corresponding path program 1 times [2018-11-23 07:29:12,981 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:12,981 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:12,997 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:13,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:13,088 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:13,095 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-23 07:29:13,096 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:13,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:13,097 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:29:13,097 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:29:13,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:29:13,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:13,098 INFO L87 Difference]: Start difference. First operand 393 states and 475 transitions. Second operand 3 states. [2018-11-23 07:29:13,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:13,210 INFO L93 Difference]: Finished difference Result 933 states and 1127 transitions. [2018-11-23 07:29:13,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:29:13,211 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2018-11-23 07:29:13,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:13,213 INFO L225 Difference]: With dead ends: 933 [2018-11-23 07:29:13,213 INFO L226 Difference]: Without dead ends: 563 [2018-11-23 07:29:13,214 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:29:13,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 563 states. [2018-11-23 07:29:13,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 563 to 560. [2018-11-23 07:29:13,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 560 states. [2018-11-23 07:29:13,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 560 states to 560 states and 666 transitions. [2018-11-23 07:29:13,246 INFO L78 Accepts]: Start accepts. Automaton has 560 states and 666 transitions. Word has length 81 [2018-11-23 07:29:13,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:13,246 INFO L480 AbstractCegarLoop]: Abstraction has 560 states and 666 transitions. [2018-11-23 07:29:13,246 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:29:13,246 INFO L276 IsEmpty]: Start isEmpty. Operand 560 states and 666 transitions. [2018-11-23 07:29:13,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-23 07:29:13,247 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:13,247 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:13,247 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:13,248 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:13,248 INFO L82 PathProgramCache]: Analyzing trace with hash 890692430, now seen corresponding path program 1 times [2018-11-23 07:29:13,248 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:13,248 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:13,264 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:13,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:13,554 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:13,580 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 07:29:13,580 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 07:29:13,582 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:29:13,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 07:29:13,583 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 07:29:13,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 07:29:13,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:29:13,583 INFO L87 Difference]: Start difference. First operand 560 states and 666 transitions. Second operand 4 states. [2018-11-23 07:29:13,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:13,647 INFO L93 Difference]: Finished difference Result 1101 states and 1312 transitions. [2018-11-23 07:29:13,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 07:29:13,647 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2018-11-23 07:29:13,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:13,649 INFO L225 Difference]: With dead ends: 1101 [2018-11-23 07:29:13,649 INFO L226 Difference]: Without dead ends: 561 [2018-11-23 07:29:13,650 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:29:13,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states. [2018-11-23 07:29:13,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 561. [2018-11-23 07:29:13,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 561 states. [2018-11-23 07:29:13,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 561 states to 561 states and 667 transitions. [2018-11-23 07:29:13,703 INFO L78 Accepts]: Start accepts. Automaton has 561 states and 667 transitions. Word has length 82 [2018-11-23 07:29:13,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:13,703 INFO L480 AbstractCegarLoop]: Abstraction has 561 states and 667 transitions. [2018-11-23 07:29:13,703 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 07:29:13,703 INFO L276 IsEmpty]: Start isEmpty. Operand 561 states and 667 transitions. [2018-11-23 07:29:13,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-11-23 07:29:13,704 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:13,704 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:13,704 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:13,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:13,705 INFO L82 PathProgramCache]: Analyzing trace with hash 770570831, now seen corresponding path program 1 times [2018-11-23 07:29:13,705 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:13,705 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:13,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:13,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:14,075 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:14,112 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 07:29:14,112 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:14,167 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 07:29:14,170 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 07:29:14,170 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FPBP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 07:29:14,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:29:14,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:29:14,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 07:29:14,266 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 07:29:14,266 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 07:29:14,310 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-23 07:29:14,327 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 4 imperfect interpolant sequences. [2018-11-23 07:29:14,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5] total 8 [2018-11-23 07:29:14,327 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 07:29:14,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 07:29:14,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:29:14,328 INFO L87 Difference]: Start difference. First operand 561 states and 667 transitions. Second operand 8 states. [2018-11-23 07:29:14,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:29:14,445 INFO L93 Difference]: Finished difference Result 1106 states and 1319 transitions. [2018-11-23 07:29:14,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:29:14,446 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 83 [2018-11-23 07:29:14,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:29:14,447 INFO L225 Difference]: With dead ends: 1106 [2018-11-23 07:29:14,447 INFO L226 Difference]: Without dead ends: 564 [2018-11-23 07:29:14,448 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-11-23 07:29:14,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 564 states. [2018-11-23 07:29:14,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 564 to 564. [2018-11-23 07:29:14,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2018-11-23 07:29:14,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 670 transitions. [2018-11-23 07:29:14,477 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 670 transitions. Word has length 83 [2018-11-23 07:29:14,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:29:14,477 INFO L480 AbstractCegarLoop]: Abstraction has 564 states and 670 transitions. [2018-11-23 07:29:14,477 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 07:29:14,477 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 670 transitions. [2018-11-23 07:29:14,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-23 07:29:14,480 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:29:14,480 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:29:14,480 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:29:14,480 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:29:14,480 INFO L82 PathProgramCache]: Analyzing trace with hash 1034230670, now seen corresponding path program 2 times [2018-11-23 07:29:14,481 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 07:29:14,481 INFO L69 tionRefinementEngine]: Using refinement strategy WalrusRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_5483f606-9f58-4043-8df0-bb20ec1d42c8/bin-2019/utaipan/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 07:29:14,498 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 07:29:15,892 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 07:29:15,892 INFO L250 tOrderPrioritization]: Conjunction of SSA is sat [2018-11-23 07:29:16,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 07:29:17,089 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv0 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv0 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv0 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv0 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv0 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv0 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv0 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv0 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv0 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv0 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv0 32), |#t~string90.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32), |old(#t~string125.base)|=(_ bv0 32), |old(#t~string125.offset)|=(_ bv0 32), |old(#t~string134.base)|=(_ bv0 32), |old(#t~string134.offset)|=(_ bv0 32), |old(#t~string140.base)|=(_ bv0 32), |old(#t~string140.offset)|=(_ bv0 32), |old(#t~string148.base)|=(_ bv0 32), |old(#t~string148.offset)|=(_ bv0 32), |old(#t~string149.base)|=(_ bv0 32), |old(#t~string149.offset)|=(_ bv0 32), |old(#t~string193.base)|=(_ bv0 32), |old(#t~string193.offset)|=(_ bv0 32), |old(#t~string195.base)|=(_ bv0 32), |old(#t~string195.offset)|=(_ bv0 32), |old(#t~string198.base)|=(_ bv0 32), |old(#t~string198.offset)|=(_ bv0 32), |old(#t~string200.base)|=(_ bv0 32), |old(#t~string200.offset)|=(_ bv0 32), |old(#t~string222.base)|=(_ bv0 32), |old(#t~string222.offset)|=(_ bv0 32), |old(#t~string90.base)|=(_ bv0 32), |old(#t~string90.offset)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.base)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.offset)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.base)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.offset)|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv0 32), |old(~ldv_init~0)|=(_ bv0 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.offset)|=(_ bv0 32), |old(~ldv_irq_line_1_0~0)|=(_ bv0 32), |old(~ldv_irq_line_1_1~0)|=(_ bv0 32), |old(~ldv_irq_line_1_2~0)|=(_ bv0 32), |old(~ldv_irq_line_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.offset)|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv0 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv0 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv0 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32;#valid := #valid[0bv32 := 0bv1];call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36bv32);call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12bv32);call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42bv32);call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42bv32);call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32bv32);call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21bv32);call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37bv32);call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10bv32);call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50bv32);call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32bv32);call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10bv32);~ldv_irq_1_2~0 := 0bv32;~LDV_IN_INTERRUPT~0 := 1bv32;~ldv_irq_1_3~0 := 0bv32;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0bv32, 0bv32;~ldv_irq_1_1~0 := 0bv32;~ldv_irq_1_0~0 := 0bv32;~ldv_irq_line_1_3~0 := 0bv32;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0bv32, 0bv32;~ldv_state_variable_0~0 := 0bv32;~ldv_state_variable_3~0 := 0bv32;~ldv_irq_line_1_0~0 := 0bv32;~ldv_state_variable_2~0 := 0bv32;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0bv32, 0bv32;~ref_cnt~0 := 0bv32;~ldv_irq_line_1_1~0 := 0bv32;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0bv32, 0bv32;~ldv_state_variable_1~0 := 0bv32;~ldv_irq_line_1_2~0 := 0bv32;~ldv_retval_2~0 := 0bv32;~ldv_retval_0~0 := 0bv32;~ldv_retval_1~0 := 0bv32;~ldv_init~0 := 0bv32;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0bv32, 0bv32;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0bv32, 0bv32;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0bv32, 0bv32;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0bv32, 0bv32;call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(8bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(16bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(24bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(32bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(40bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(48bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(56bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(64bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(72bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(80bv32, ~#tegra_rtc_ops~0.offset), 8bv32);call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(8bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(16bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(24bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(32bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(40bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(48bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(56bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(64bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~intINTTYPE1(0bv8, ~#tegra_rtc_driver~0.base, ~bvadd32(72bv32, ~#tegra_rtc_driver~0.offset), 1bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(73bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(81bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(89bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(97bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(105bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(113bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(121bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(129bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(137bv32, ~#tegra_rtc_driver~0.offset), 8bv32);call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(145bv32, ~#tegra_rtc_driver~0.offset), 8bv32); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32), |old(#t~string125.base)|=(_ bv0 32), |old(#t~string125.offset)|=(_ bv0 32), |old(#t~string134.base)|=(_ bv0 32), |old(#t~string134.offset)|=(_ bv0 32), |old(#t~string140.base)|=(_ bv0 32), |old(#t~string140.offset)|=(_ bv0 32), |old(#t~string148.base)|=(_ bv0 32), |old(#t~string148.offset)|=(_ bv0 32), |old(#t~string149.base)|=(_ bv0 32), |old(#t~string149.offset)|=(_ bv0 32), |old(#t~string193.base)|=(_ bv0 32), |old(#t~string193.offset)|=(_ bv0 32), |old(#t~string195.base)|=(_ bv0 32), |old(#t~string195.offset)|=(_ bv0 32), |old(#t~string198.base)|=(_ bv0 32), |old(#t~string198.offset)|=(_ bv0 32), |old(#t~string200.base)|=(_ bv0 32), |old(#t~string200.offset)|=(_ bv0 32), |old(#t~string222.base)|=(_ bv0 32), |old(#t~string222.offset)|=(_ bv0 32), |old(#t~string90.base)|=(_ bv0 32), |old(#t~string90.offset)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.base)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.offset)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.base)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.offset)|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv0 32), |old(~ldv_init~0)|=(_ bv0 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.offset)|=(_ bv0 32), |old(~ldv_irq_line_1_0~0)|=(_ bv0 32), |old(~ldv_irq_line_1_1~0)|=(_ bv0 32), |old(~ldv_irq_line_1_2~0)|=(_ bv0 32), |old(~ldv_irq_line_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(#NULL.base)|=(_ bv0 32), |old(#NULL.offset)|=(_ bv0 32), |old(#t~string125.base)|=(_ bv0 32), |old(#t~string125.offset)|=(_ bv0 32), |old(#t~string134.base)|=(_ bv0 32), |old(#t~string134.offset)|=(_ bv0 32), |old(#t~string140.base)|=(_ bv0 32), |old(#t~string140.offset)|=(_ bv0 32), |old(#t~string148.base)|=(_ bv0 32), |old(#t~string148.offset)|=(_ bv0 32), |old(#t~string149.base)|=(_ bv0 32), |old(#t~string149.offset)|=(_ bv0 32), |old(#t~string193.base)|=(_ bv0 32), |old(#t~string193.offset)|=(_ bv0 32), |old(#t~string195.base)|=(_ bv0 32), |old(#t~string195.offset)|=(_ bv0 32), |old(#t~string198.base)|=(_ bv0 32), |old(#t~string198.offset)|=(_ bv0 32), |old(#t~string200.base)|=(_ bv0 32), |old(#t~string200.offset)|=(_ bv0 32), |old(#t~string222.base)|=(_ bv0 32), |old(#t~string222.offset)|=(_ bv0 32), |old(#t~string90.base)|=(_ bv0 32), |old(#t~string90.offset)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.base)|=(_ bv0 32), |old(~#tegra_rtc_driver~0.offset)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.base)|=(_ bv0 32), |old(~#tegra_rtc_ops~0.offset)|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv0 32), |old(~ldv_init~0)|=(_ bv0 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_0~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_1~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_2~0.offset)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.base)|=(_ bv0 32), |old(~ldv_irq_data_1_3~0.offset)|=(_ bv0 32), |old(~ldv_irq_line_1_0~0)|=(_ bv0 32), |old(~ldv_irq_line_1_1~0)|=(_ bv0 32), |old(~ldv_irq_line_1_2~0)|=(_ bv0 32), |old(~ldv_irq_line_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group0~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group1~0.offset)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.base)|=(_ bv0 32), |old(~tegra_rtc_ops_group2~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #874#return; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret277 := main(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset;havoc ~tmp~27.base, ~tmp~27.offset;havoc ~ldvarg0~0;havoc ~tmp___0~8;call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4bv32);havoc ~tmp___1~5;havoc ~tmp___2~1;havoc ~tmp___3~1;havoc ~tmp___4~1; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136bv32); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv136 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~size := #in~size;havoc ~p~1.base, ~p~1.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~1;~tmp___0~1 := #t~nondet12;havoc #t~nondet12; VAL [ldv_zalloc_~size=(_ bv136 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv136 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 != ~tmp___0~1;#res.base, #res.offset := 0bv32, 0bv32; VAL [ldv_zalloc_~size=(_ bv136 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv136 32), |ldv_zalloc_#res.base|=(_ bv0 32), |ldv_zalloc_#res.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [ldv_zalloc_~size=(_ bv136 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv136 32), |ldv_zalloc_#res.base|=(_ bv0 32), |ldv_zalloc_#res.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #738#return; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~ret237.base|=(_ bv0 32), |main_#t~ret237.offset|=(_ bv0 32), |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset;havoc #t~ret237.base, #t~ret237.offset;~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset;~tmp___0~8 := #t~nondet238;havoc #t~nondet238;~ldvarg0~0 := ~tmp___0~8;call ldv_initialize(); VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0bv32, 4bv32); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] #t~loopctr278 := 0bv32; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv0 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume ~bvslt32(#t~loopctr278, #amount);#memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv1 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume ~bvslt32(#t~loopctr278, #amount);#memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv2 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume ~bvslt32(#t~loopctr278, #amount);#memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv3 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume ~bvslt32(#t~loopctr278, #amount);#memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])];#t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv4 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !~bvslt32(#t~loopctr278, #amount); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv4 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |#Ultimate.C_memset_#amount|=(_ bv4 32), |#Ultimate.C_memset_#ptr.base|=(_ bv67108864 32), |#Ultimate.C_memset_#ptr.offset|=(_ bv0 32), |#Ultimate.C_memset_#res.base|=(_ bv67108864 32), |#Ultimate.C_memset_#res.offset|=(_ bv0 32), |#Ultimate.C_memset_#t~loopctr278|=(_ bv4 32), |#Ultimate.C_memset_#value|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #740#return; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~memset~res239.base|=(_ bv67108864 32), |main_#t~memset~res239.offset|=(_ bv0 32), |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv0 32), ~ldv_state_variable_1~0=(_ bv0 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] havoc #t~memset~res239.base, #t~memset~res239.offset;~ldv_state_variable_1~0 := 1bv32;~ref_cnt~0 := 0bv32;~ldv_state_variable_0~0 := 1bv32;~ldv_state_variable_3~0 := 0bv32;~ldv_state_variable_2~0 := 0bv32; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch241; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 != ~ldv_state_variable_0~0;~tmp___2~1 := #t~nondet242;havoc #t~nondet242;#t~switch243 := 0bv32 == ~tmp___2~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch243;#t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch243; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 1bv32 == ~ldv_state_variable_0~0; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret244 := tegra_rtc_init(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] havoc ~tmp~22;call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset);~tmp~22 := #t~ret223;havoc #t~ret223;#res := ~tmp~22; VAL [tegra_rtc_init_~tmp~22=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_init_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [tegra_rtc_init_~tmp~22=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_init_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #746#return; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~ret244|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~ldv_retval_0~0 := #t~ret244;havoc #t~ret244; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv1 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv0 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 == ~ldv_retval_0~0;~ldv_state_variable_0~0 := 3bv32;~ldv_state_variable_2~0 := 1bv32; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call ldv_initialize_platform_driver_2(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] havoc ~tmp~26.base, ~tmp~26.offset; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624bv32); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv624 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~size := #in~size;havoc ~p~1.base, ~p~1.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~1;~tmp___0~1 := #t~nondet12;havoc #t~nondet12; VAL [ldv_zalloc_~size=(_ bv624 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv624 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 != ~tmp___0~1;#res.base, #res.offset := 0bv32, 0bv32; VAL [ldv_zalloc_~size=(_ bv624 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv624 32), |ldv_zalloc_#res.base|=(_ bv0 32), |ldv_zalloc_#res.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [ldv_zalloc_~size=(_ bv624 32), ldv_zalloc_~tmp___0~1=(_ bv1 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_zalloc_#in~size|=(_ bv624 32), |ldv_zalloc_#res.base|=(_ bv0 32), |ldv_zalloc_#res.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #804#return; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |ldv_initialize_platform_driver_2_#t~ret236.base|=(_ bv0 32), |ldv_initialize_platform_driver_2_#t~ret236.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset;havoc #t~ret236.base, #t~ret236.offset;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [ldv_initialize_platform_driver_2_~tmp~26.base=(_ bv0 32), ldv_initialize_platform_driver_2_~tmp~26.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [ldv_initialize_platform_driver_2_~tmp~26.base=(_ bv0 32), ldv_initialize_platform_driver_2_~tmp~26.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #748#return; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !(0bv32 != ~ldv_retval_0~0); VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv1 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch241; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 != ~ldv_state_variable_2~0;~tmp___4~1 := #t~nondet260;havoc #t~nondet260;#t~switch261 := 0bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch261; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv1 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv0 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 1bv32 == ~ldv_state_variable_2~0;call #t~ret268 := ldv_probe_2();havoc #t~ret268;~ldv_state_variable_2~0 := 2bv32;~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch241; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv4 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 0bv32 != ~ldv_state_variable_2~0;~tmp___4~1 := #t~nondet260;havoc #t~nondet260;#t~switch261 := 0bv32 == ~tmp___4~1; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume #t~switch261; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !(4bv32 == ~ldv_state_variable_2~0); VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume 2bv32 == ~ldv_state_variable_2~0; VAL [main_~ldvarg0~0=(_ bv0 32), main_~ldvarg1~0.base=(_ bv0 32), main_~ldvarg1~0.offset=(_ bv0 32), main_~tmp___0~8=(_ bv0 32), main_~tmp___1~5=(_ bv3 32), main_~tmp___2~1=(_ bv1 32), main_~tmp___4~1=(_ bv0 32), main_~tmp~27.base=(_ bv0 32), main_~tmp~27.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=(_ bv67108864 32), |main_~#ldvarg2~0.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_shutdown_#in~pdev.base|=(_ bv0 32), |tegra_rtc_shutdown_#in~pdev.offset|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [tegra_rtc_shutdown_~pdev.base=(_ bv0 32), tegra_rtc_shutdown_~pdev.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_shutdown_#in~pdev.base|=(_ bv0 32), |tegra_rtc_shutdown_#in~pdev.offset|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, ~bvadd32(12bv32, ~pdev.offset), 0bv32); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.base|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.offset|=(_ bv12 32), |tegra_rtc_alarm_irq_enable_#in~enabled|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;~enabled := #in~enabled;havoc ~info~4.base, ~info~4.offset;havoc ~tmp~14.base, ~tmp~14.offset;havoc ~status~0;havoc ~sl_irq_flags~1;havoc ~__v~3;havoc ~__v___0~3;call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset);~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset;havoc #t~ret107.base, #t~ret107.offset;~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [tegra_rtc_alarm_irq_enable_~dev.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~dev.offset=(_ bv12 32), tegra_rtc_alarm_irq_enable_~enabled=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.offset=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.base|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.offset|=(_ bv12 32), |tegra_rtc_alarm_irq_enable_#in~enabled|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;havoc ~info~0.base, ~info~0.offset;havoc ~tmp~10.base, ~tmp~10.offset;havoc ~retries~0;havoc ~tmp___0~2;havoc ~tmp___1~0;call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset);~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset;havoc #t~ret87.base, #t~ret87.offset;~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset;~retries~0 := 500bv32; VAL [tegra_rtc_wait_while_busy_~dev.base=(_ bv0 32), tegra_rtc_wait_while_busy_~dev.offset=(_ bv12 32), tegra_rtc_wait_while_busy_~info~0.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~info~0.offset=(_ bv4294967283 32), tegra_rtc_wait_while_busy_~retries~0=(_ bv500 32), tegra_rtc_wait_while_busy_~tmp~10.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~tmp~10.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_check_busy_#in~info.base|=(_ bv67108865 32), |tegra_rtc_check_busy_#in~info.offset|=(_ bv4294967283 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~info.base, ~info.offset := #in~info.base, #in~info.offset;havoc ~__v~0;havoc ~__v___0~0;call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, ~bvadd32(16bv32, ~info.offset), 8bv32);call #t~mem86 := read~intINTTYPE4(#t~mem85.base, ~bvadd32(16bv32, #t~mem85.offset), 4bv32);~__v___0~0 := #t~mem86;havoc #t~mem85.base, #t~mem85.offset;havoc #t~mem86;~__v~0 := ~__v___0~0;#res := ~bvand32(1bv32, ~__v~0); VAL [tegra_rtc_check_busy_~__v___0~0=(_ bv0 32), tegra_rtc_check_busy_~__v~0=(_ bv0 32), tegra_rtc_check_busy_~info.base=(_ bv67108865 32), tegra_rtc_check_busy_~info.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_check_busy_#in~info.base|=(_ bv67108865 32), |tegra_rtc_check_busy_#in~info.offset|=(_ bv4294967283 32), |tegra_rtc_check_busy_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [tegra_rtc_check_busy_~__v___0~0=(_ bv0 32), tegra_rtc_check_busy_~__v~0=(_ bv0 32), tegra_rtc_check_busy_~info.base=(_ bv67108865 32), tegra_rtc_check_busy_~info.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_check_busy_#in~info.base|=(_ bv67108865 32), |tegra_rtc_check_busy_#in~info.offset|=(_ bv4294967283 32), |tegra_rtc_check_busy_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #850#return; VAL [tegra_rtc_wait_while_busy_~dev.base=(_ bv0 32), tegra_rtc_wait_while_busy_~dev.offset=(_ bv12 32), tegra_rtc_wait_while_busy_~info~0.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~info~0.offset=(_ bv4294967283 32), tegra_rtc_wait_while_busy_~retries~0=(_ bv500 32), tegra_rtc_wait_while_busy_~tmp~10.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~tmp~10.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |tegra_rtc_wait_while_busy_#t~ret88|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] ~tmp___1~0 := #t~ret88;havoc #t~ret88; VAL [tegra_rtc_wait_while_busy_~dev.base=(_ bv0 32), tegra_rtc_wait_while_busy_~dev.offset=(_ bv12 32), tegra_rtc_wait_while_busy_~info~0.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~info~0.offset=(_ bv4294967283 32), tegra_rtc_wait_while_busy_~retries~0=(_ bv500 32), tegra_rtc_wait_while_busy_~tmp___1~0=(_ bv0 32), tegra_rtc_wait_while_busy_~tmp~10.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~tmp~10.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !(0bv32 != ~tmp___1~0);#res := 0bv32; VAL [tegra_rtc_wait_while_busy_~dev.base=(_ bv0 32), tegra_rtc_wait_while_busy_~dev.offset=(_ bv12 32), tegra_rtc_wait_while_busy_~info~0.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~info~0.offset=(_ bv4294967283 32), tegra_rtc_wait_while_busy_~retries~0=(_ bv500 32), tegra_rtc_wait_while_busy_~tmp___1~0=(_ bv0 32), tegra_rtc_wait_while_busy_~tmp~10.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~tmp~10.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |tegra_rtc_wait_while_busy_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume true; VAL [tegra_rtc_wait_while_busy_~dev.base=(_ bv0 32), tegra_rtc_wait_while_busy_~dev.offset=(_ bv12 32), tegra_rtc_wait_while_busy_~info~0.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~info~0.offset=(_ bv4294967283 32), tegra_rtc_wait_while_busy_~retries~0=(_ bv500 32), tegra_rtc_wait_while_busy_~tmp___1~0=(_ bv0 32), tegra_rtc_wait_while_busy_~tmp~10.base=(_ bv67108865 32), tegra_rtc_wait_while_busy_~tmp~10.offset=(_ bv4294967283 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.base|=(_ bv0 32), |tegra_rtc_wait_while_busy_#in~dev.offset|=(_ bv12 32), |tegra_rtc_wait_while_busy_#res|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] RET #854#return; VAL [tegra_rtc_alarm_irq_enable_~dev.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~dev.offset=(_ bv12 32), tegra_rtc_alarm_irq_enable_~enabled=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.offset=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.base|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.offset|=(_ bv12 32), |tegra_rtc_alarm_irq_enable_#in~enabled|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#t~ret108|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] havoc #t~ret108; VAL [tegra_rtc_alarm_irq_enable_~dev.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~dev.offset=(_ bv12 32), tegra_rtc_alarm_irq_enable_~enabled=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~info~4.offset=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.base=(_ bv0 32), tegra_rtc_alarm_irq_enable_~tmp~14.offset=(_ bv0 32), |#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.base|=(_ bv0 32), |tegra_rtc_alarm_irq_enable_#in~dev.offset|=(_ bv12 32), |tegra_rtc_alarm_irq_enable_#in~enabled|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call ldv_spin_lock_check(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !(1bv32 == ~ldv_init~0); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call ldv_error(); VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] assume !false; VAL [|#NULL.base|=(_ bv0 32), |#NULL.offset|=(_ bv0 32), |#t~string125.base|=(_ bv4294963700 32), |#t~string125.offset|=(_ bv0 32), |#t~string134.base|=(_ bv4294963699 32), |#t~string134.offset|=(_ bv0 32), |#t~string140.base|=(_ bv4294963704 32), |#t~string140.offset|=(_ bv0 32), |#t~string148.base|=(_ bv4294963703 32), |#t~string148.offset|=(_ bv0 32), |#t~string149.base|=(_ bv4294963706 32), |#t~string149.offset|=(_ bv0 32), |#t~string193.base|=(_ bv4294963702 32), |#t~string193.offset|=(_ bv0 32), |#t~string195.base|=(_ bv4294965748 32), |#t~string195.offset|=(_ bv0 32), |#t~string198.base|=(_ bv4294963707 32), |#t~string198.offset|=(_ bv0 32), |#t~string200.base|=(_ bv4294963701 32), |#t~string200.offset|=(_ bv0 32), |#t~string222.base|=(_ bv4294963698 32), |#t~string222.offset|=(_ bv0 32), |#t~string90.base|=(_ bv3875469542 32), |#t~string90.offset|=(_ bv0 32), |old(~LDV_IN_INTERRUPT~0)|=(_ bv1 32), |old(~ldv_irq_1_0~0)|=(_ bv0 32), |old(~ldv_irq_1_1~0)|=(_ bv0 32), |old(~ldv_irq_1_2~0)|=(_ bv0 32), |old(~ldv_irq_1_3~0)|=(_ bv0 32), |old(~ldv_retval_0~0)|=(_ bv0 32), |old(~ldv_retval_1~0)|=(_ bv0 32), |old(~ldv_retval_2~0)|=(_ bv0 32), |old(~ldv_state_variable_0~0)|=(_ bv0 32), |old(~ldv_state_variable_1~0)|=(_ bv0 32), |old(~ldv_state_variable_2~0)|=(_ bv0 32), |old(~ldv_state_variable_3~0)|=(_ bv0 32), |old(~ref_cnt~0)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.base)|=(_ bv0 32), |old(~tegra_rtc_driver_group0~0.offset)|=(_ bv0 32), |~#__this_module~0.base|=(_ bv0 32), |~#__this_module~0.offset|=(_ bv0 32), |~#tegra_rtc_driver~0.base|=(_ bv2269114822 32), |~#tegra_rtc_driver~0.offset|=(_ bv0 32), |~#tegra_rtc_ops~0.base|=(_ bv4261409267 32), |~#tegra_rtc_ops~0.offset|=(_ bv0 32), ~LDV_IN_INTERRUPT~0=(_ bv1 32), ~ldv_init~0=(_ bv0 32), ~ldv_irq_1_0~0=(_ bv0 32), ~ldv_irq_1_1~0=(_ bv0 32), ~ldv_irq_1_2~0=(_ bv0 32), ~ldv_irq_1_3~0=(_ bv0 32), ~ldv_irq_data_1_0~0.base=(_ bv0 32), ~ldv_irq_data_1_0~0.offset=(_ bv0 32), ~ldv_irq_data_1_1~0.base=(_ bv0 32), ~ldv_irq_data_1_1~0.offset=(_ bv0 32), ~ldv_irq_data_1_2~0.base=(_ bv0 32), ~ldv_irq_data_1_2~0.offset=(_ bv0 32), ~ldv_irq_data_1_3~0.base=(_ bv0 32), ~ldv_irq_data_1_3~0.offset=(_ bv0 32), ~ldv_irq_line_1_0~0=(_ bv0 32), ~ldv_irq_line_1_1~0=(_ bv0 32), ~ldv_irq_line_1_2~0=(_ bv0 32), ~ldv_irq_line_1_3~0=(_ bv0 32), ~ldv_retval_0~0=(_ bv0 32), ~ldv_retval_1~0=(_ bv0 32), ~ldv_retval_2~0=(_ bv0 32), ~ldv_state_variable_0~0=(_ bv3 32), ~ldv_state_variable_1~0=(_ bv1 32), ~ldv_state_variable_2~0=(_ bv2 32), ~ldv_state_variable_3~0=(_ bv0 32), ~ref_cnt~0=(_ bv1 32), ~tegra_rtc_driver_group0~0.base=(_ bv0 32), ~tegra_rtc_driver_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group0~0.base=(_ bv0 32), ~tegra_rtc_ops_group0~0.offset=(_ bv0 32), ~tegra_rtc_ops_group1~0.base=(_ bv0 32), ~tegra_rtc_ops_group1~0.offset=(_ bv0 32), ~tegra_rtc_ops_group2~0.base=(_ bv0 32), ~tegra_rtc_ops_group2~0.offset=(_ bv0 32)] [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=0bv32, #t~string125.offset=0bv32, #t~string134.base=0bv32, #t~string134.offset=0bv32, #t~string140.base=0bv32, #t~string140.offset=0bv32, #t~string148.base=0bv32, #t~string148.offset=0bv32, #t~string149.base=0bv32, #t~string149.offset=0bv32, #t~string193.base=0bv32, #t~string193.offset=0bv32, #t~string195.base=0bv32, #t~string195.offset=0bv32, #t~string198.base=0bv32, #t~string198.offset=0bv32, #t~string200.base=0bv32, #t~string200.offset=0bv32, #t~string222.base=0bv32, #t~string222.offset=0bv32, #t~string90.base=0bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#tegra_rtc_driver~0.base=0bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=0bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; [L1905] call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36bv32); [L2072] call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12bv32); [L2150] call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42bv32); [L2159] call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42bv32); [L2175] call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32bv32); [L2189] call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21bv32); [L2211] call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37bv32); [L2218] call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10bv32); [L2220] call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50bv32); [L2226] call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32bv32); [L2323] call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0bv32, 0bv32; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0bv32, 0bv32; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0bv32, 0bv32; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0bv32, 0bv32; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0bv32, 0bv32; [L1723] ~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0bv32, 0bv32; [L1730] ~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0bv32, 0bv32; [L1734] ~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0bv32, 0bv32; [L2123-L2125] call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(8bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(16bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(24bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(32bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(40bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(48bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(56bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(64bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(72bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(80bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2322-L2323] call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(8bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(16bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(24bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(32bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(40bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(48bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(56bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(64bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~intINTTYPE1(0bv8, ~#tegra_rtc_driver~0.base, ~bvadd32(72bv32, ~#tegra_rtc_driver~0.offset), 1bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(73bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(81bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(89bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(97bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(105bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(113bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(121bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(129bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(137bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(145bv32, ~#tegra_rtc_driver~0.offset), 8bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2518] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset; [L2519] havoc ~tmp~27.base, ~tmp~27.offset; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2529] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1641-L1648] assume 0bv32 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0bv32, 0bv32; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1584] ensures true; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret237.base=0bv32, #t~ret237.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2529] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset; [L2529] havoc #t~ret237.base, #t~ret237.offset; [L2530] ~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] call ldv_initialize(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2534] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=1bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=2bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=3bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume !~bvslt32(#t~loopctr278, #amount); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #res.base=67108864bv32, #res.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2534] RET call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0bv32, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~memset~res239.base=67108864bv32, #t~memset~res239.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2534] havoc #t~memset~res239.base, #t~memset~res239.offset; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2551-L2589] assume 0bv32 != ~ldv_state_variable_0~0; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2554] assume !#t~switch243; [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2563] assume #t~switch243; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2564-L2581] assume 1bv32 == ~ldv_state_variable_0~0; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2326] havoc ~tmp~22; [L2329] call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~22=0bv32] [L2324-L2332] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret244=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2566-L2572] assume 0bv32 == ~ldv_retval_0~0; [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2476] havoc ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2479] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1641-L1648] assume 0bv32 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0bv32, 0bv32; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1584] ensures true; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret236.base=0bv32, #t~ret236.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2479] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset; [L2479] havoc #t~ret236.base, #t~ret236.offset; [L2480] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~26.base=0bv32, ~tmp~26.offset=0bv32] [L1740] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~26.base=0bv32, ~tmp~26.offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2573-L2578] assume !(0bv32 != ~ldv_retval_0~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2699] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2700-L2779] assume 0bv32 != ~ldv_state_variable_2~0; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2703] assume !#t~switch261; [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2717] assume !#t~switch261; [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2729] assume !#t~switch261; [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2752] assume !#t~switch261; [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2764] assume #t~switch261; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2765-L2771] assume 1bv32 == ~ldv_state_variable_2~0; [L2766] call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2699] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2700-L2779] assume 0bv32 != ~ldv_state_variable_2~0; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2703] assume #t~switch261; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2704-L2709] assume !(4bv32 == ~ldv_state_variable_2~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2710-L2715] assume 2bv32 == ~ldv_state_variable_2~0; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [#in~pdev.base=0bv32, #in~pdev.offset=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2313-L2321] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [#in~pdev.base=0bv32, #in~pdev.offset=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev.base=0bv32, ~pdev.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, ~bvadd32(12bv32, ~pdev.offset), 0bv32); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2004-L2033] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4.base, ~info~4.offset; [L2007] havoc ~tmp~14.base, ~tmp~14.offset; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L2014] ~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset; [L2014] havoc #t~ret107.base, #t~ret107.offset; [L2015] ~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1873-L1908] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L1875] havoc ~info~0.base, ~info~0.offset; [L1876] havoc ~tmp~10.base, ~tmp~10.offset; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L1882] ~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset; [L1882] havoc #t~ret87.base, #t~ret87.offset; [L1883] ~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset; [L1884] ~retries~0 := 500bv32; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1861-L1872] ~info.base, ~info.offset := #in~info.base, #in~info.offset; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, ~bvadd32(16bv32, ~info.offset), 8bv32); [L1867] call #t~mem86 := read~intINTTYPE4(#t~mem85.base, ~bvadd32(16bv32, #t~mem85.offset), 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85.base, #t~mem85.offset; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info.base=67108865bv32, ~info.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1861-L1872] ensures true; VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info.base=67108865bv32, ~info.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~ret88=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1897-L1901] assume !(0bv32 != ~tmp___1~0); [L1903] #res := 0bv32; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1873-L1908] ensures true; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~ret108=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2962-L2966] assume !(1bv32 == ~ldv_init~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1684] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] ----- [2018-11-23 07:29:17,584 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=0bv32, #t~string125.offset=0bv32, #t~string134.base=0bv32, #t~string134.offset=0bv32, #t~string140.base=0bv32, #t~string140.offset=0bv32, #t~string148.base=0bv32, #t~string148.offset=0bv32, #t~string149.base=0bv32, #t~string149.offset=0bv32, #t~string193.base=0bv32, #t~string193.offset=0bv32, #t~string195.base=0bv32, #t~string195.offset=0bv32, #t~string198.base=0bv32, #t~string198.offset=0bv32, #t~string200.base=0bv32, #t~string200.offset=0bv32, #t~string222.base=0bv32, #t~string222.offset=0bv32, #t~string90.base=0bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#tegra_rtc_driver~0.base=0bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=0bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] #NULL.base, #NULL.offset := 0bv32, 0bv32; [?] #valid := #valid[0bv32 := 0bv1]; [L1905] call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36bv32); [L2072] call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12bv32); [L2150] call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42bv32); [L2159] call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42bv32); [L2175] call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32bv32); [L2189] call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21bv32); [L2211] call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37bv32); [L2218] call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10bv32); [L2220] call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50bv32); [L2226] call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32bv32); [L2323] call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0bv32, 0bv32; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0bv32, 0bv32; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0bv32, 0bv32; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0bv32, 0bv32; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0bv32, 0bv32; [L1723] ~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0bv32, 0bv32; [L1730] ~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0bv32, 0bv32; [L1734] ~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0bv32, 0bv32; [L2123-L2125] call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(8bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(16bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(24bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(32bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(40bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(48bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(56bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(64bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_ops~0.base, ~bvadd32(72bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, ~bvadd32(80bv32, ~#tegra_rtc_ops~0.offset), 8bv32); [L2322-L2323] call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(8bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(16bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(24bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(32bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(40bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(48bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, ~bvadd32(56bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(64bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~intINTTYPE1(0bv8, ~#tegra_rtc_driver~0.base, ~bvadd32(72bv32, ~#tegra_rtc_driver~0.offset), 1bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(73bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(81bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(89bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(97bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(105bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(113bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(121bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(129bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(137bv32, ~#tegra_rtc_driver~0.offset), 8bv32); [L2322-L2323] call write~init~$Pointer$(0bv32, 0bv32, ~#tegra_rtc_driver~0.base, ~bvadd32(145bv32, ~#tegra_rtc_driver~0.offset), 8bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(#NULL.base)=0bv32, old(#NULL.offset)=0bv32, old(#t~string125.base)=0bv32, old(#t~string125.offset)=0bv32, old(#t~string134.base)=0bv32, old(#t~string134.offset)=0bv32, old(#t~string140.base)=0bv32, old(#t~string140.offset)=0bv32, old(#t~string148.base)=0bv32, old(#t~string148.offset)=0bv32, old(#t~string149.base)=0bv32, old(#t~string149.offset)=0bv32, old(#t~string193.base)=0bv32, old(#t~string193.offset)=0bv32, old(#t~string195.base)=0bv32, old(#t~string195.offset)=0bv32, old(#t~string198.base)=0bv32, old(#t~string198.offset)=0bv32, old(#t~string200.base)=0bv32, old(#t~string200.offset)=0bv32, old(#t~string222.base)=0bv32, old(#t~string222.offset)=0bv32, old(#t~string90.base)=0bv32, old(#t~string90.offset)=0bv32, old(~#tegra_rtc_driver~0.base)=0bv32, old(~#tegra_rtc_driver~0.offset)=0bv32, old(~#tegra_rtc_ops~0.base)=0bv32, old(~#tegra_rtc_ops~0.offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0.base)=0bv32, old(~ldv_irq_data_1_0~0.offset)=0bv32, old(~ldv_irq_data_1_1~0.base)=0bv32, old(~ldv_irq_data_1_1~0.offset)=0bv32, old(~ldv_irq_data_1_2~0.base)=0bv32, old(~ldv_irq_data_1_2~0.offset)=0bv32, old(~ldv_irq_data_1_3~0.base)=0bv32, old(~ldv_irq_data_1_3~0.offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group0~0.base)=0bv32, old(~tegra_rtc_ops_group0~0.offset)=0bv32, old(~tegra_rtc_ops_group1~0.base)=0bv32, old(~tegra_rtc_ops_group1~0.offset)=0bv32, old(~tegra_rtc_ops_group2~0.base)=0bv32, old(~tegra_rtc_ops_group2~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2518] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset; [L2519] havoc ~tmp~27.base, ~tmp~27.offset; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2529] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1641-L1648] assume 0bv32 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0bv32, 0bv32; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1584] ensures true; VAL [#in~size=136bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret237.base=0bv32, #t~ret237.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2529] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset; [L2529] havoc #t~ret237.base, #t~ret237.offset; [L2530] ~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] call ldv_initialize(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2534] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=1bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=2bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=3bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume ~bvslt32(#t~loopctr278, #amount); [?] #memory_int := #memory_int[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := 0bv32], #memory_$Pointer$.offset[#ptr.base,~bvadd32(#ptr.offset, #t~loopctr278) := ~zero_extendFrom8To32(#value[8:0])]; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] assume !~bvslt32(#t~loopctr278, #amount); VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [#amount=4bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #ptr.base=67108864bv32, #ptr.offset=0bv32, #res.base=67108864bv32, #res.offset=0bv32, #t~loopctr278=4bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2534] RET call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0bv32, 4bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~memset~res239.base=67108864bv32, #t~memset~res239.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2534] havoc #t~memset~res239.base, #t~memset~res239.offset; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2551-L2589] assume 0bv32 != ~ldv_state_variable_0~0; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2554] assume !#t~switch243; [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2563] assume #t~switch243; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2564-L2581] assume 1bv32 == ~ldv_state_variable_0~0; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2326] havoc ~tmp~22; [L2329] call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~22=0bv32] [L2324-L2332] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret244=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2566-L2572] assume 0bv32 == ~ldv_retval_0~0; [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2476] havoc ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2479] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1641-L1648] assume 0bv32 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0bv32, 0bv32; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L1584] ensures true; VAL [#in~size=624bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res.base=0bv32, #res.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624bv32); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~ret236.base=0bv32, #t~ret236.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2479] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset; [L2479] havoc #t~ret236.base, #t~ret236.offset; [L2480] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~26.base=0bv32, ~tmp~26.offset=0bv32] [L1740] ensures true; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~26.base=0bv32, ~tmp~26.offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2573-L2578] assume !(0bv32 != ~ldv_retval_0~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2699] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2700-L2779] assume 0bv32 != ~ldv_state_variable_2~0; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2703] assume !#t~switch261; [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2717] assume !#t~switch261; [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2729] assume !#t~switch261; [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2752] assume !#t~switch261; [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2764] assume #t~switch261; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2765-L2771] assume 1bv32 == ~ldv_state_variable_2~0; [L2766] call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2699] assume #t~switch241; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2700-L2779] assume 0bv32 != ~ldv_state_variable_2~0; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2703] assume #t~switch261; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2704-L2709] assume !(4bv32 == ~ldv_state_variable_2~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2710-L2715] assume 2bv32 == ~ldv_state_variable_2~0; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#ldvarg2~0.base=67108864bv32, ~#ldvarg2~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0.base=0bv32, ~ldvarg1~0.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27.base=0bv32, ~tmp~27.offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [#in~pdev.base=0bv32, #in~pdev.offset=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2313-L2321] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [#in~pdev.base=0bv32, #in~pdev.offset=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev.base=0bv32, ~pdev.offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, ~bvadd32(12bv32, ~pdev.offset), 0bv32); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2004-L2033] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4.base, ~info~4.offset; [L2007] havoc ~tmp~14.base, ~tmp~14.offset; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L2014] ~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset; [L2014] havoc #t~ret107.base, #t~ret107.offset; [L2015] ~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1873-L1908] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L1875] havoc ~info~0.base, ~info~0.offset; [L1876] havoc ~tmp~10.base, ~tmp~10.offset; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L1882] ~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset; [L1882] havoc #t~ret87.base, #t~ret87.offset; [L1883] ~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset; [L1884] ~retries~0 := 500bv32; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1861-L1872] ~info.base, ~info.offset := #in~info.base, #in~info.offset; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, ~bvadd32(16bv32, ~info.offset), 8bv32); [L1867] call #t~mem86 := read~intINTTYPE4(#t~mem85.base, ~bvadd32(16bv32, #t~mem85.offset), 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85.base, #t~mem85.offset; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info.base=67108865bv32, ~info.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1861-L1872] ensures true; VAL [#in~info.base=67108865bv32, #in~info.offset=4294967283bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info.base=67108865bv32, ~info.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~ret88=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1897-L1901] assume !(0bv32 != ~tmp___1~0); [L1903] #res := 0bv32; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L1873-L1908] ensures true; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #res=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~info~0.base=67108865bv32, ~info~0.offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10.base=67108865bv32, ~tmp~10.offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~ret108=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev.base=0bv32, #in~dev.offset=12bv32, #in~enabled=0bv32, #NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~dev.base=0bv32, ~dev.offset=12bv32, ~enabled=0bv32, ~info~4.base=0bv32, ~info~4.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32, ~tmp~14.base=0bv32, ~tmp~14.offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2962-L2966] assume !(1bv32 == ~ldv_init~0); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [L1684] assert false; VAL [#NULL.base=0bv32, #NULL.offset=0bv32, #t~string125.base=4294963700bv32, #t~string125.offset=0bv32, #t~string134.base=4294963699bv32, #t~string134.offset=0bv32, #t~string140.base=4294963704bv32, #t~string140.offset=0bv32, #t~string148.base=4294963703bv32, #t~string148.offset=0bv32, #t~string149.base=4294963706bv32, #t~string149.offset=0bv32, #t~string193.base=4294963702bv32, #t~string193.offset=0bv32, #t~string195.base=4294965748bv32, #t~string195.offset=0bv32, #t~string198.base=4294963707bv32, #t~string198.offset=0bv32, #t~string200.base=4294963701bv32, #t~string200.offset=0bv32, #t~string222.base=4294963698bv32, #t~string222.offset=0bv32, #t~string90.base=3875469542bv32, #t~string90.offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0.base)=0bv32, old(~tegra_rtc_driver_group0~0.offset)=0bv32, ~#__this_module~0.base=0bv32, ~#__this_module~0.offset=0bv32, ~#tegra_rtc_driver~0.base=2269114822bv32, ~#tegra_rtc_driver~0.offset=0bv32, ~#tegra_rtc_ops~0.base=4261409267bv32, ~#tegra_rtc_ops~0.offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0.base=0bv32, ~ldv_irq_data_1_0~0.offset=0bv32, ~ldv_irq_data_1_1~0.base=0bv32, ~ldv_irq_data_1_1~0.offset=0bv32, ~ldv_irq_data_1_2~0.base=0bv32, ~ldv_irq_data_1_2~0.offset=0bv32, ~ldv_irq_data_1_3~0.base=0bv32, ~ldv_irq_data_1_3~0.offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0.base=0bv32, ~tegra_rtc_driver_group0~0.offset=0bv32, ~tegra_rtc_ops_group0~0.base=0bv32, ~tegra_rtc_ops_group0~0.offset=0bv32, ~tegra_rtc_ops_group1~0.base=0bv32, ~tegra_rtc_ops_group1~0.offset=0bv32, ~tegra_rtc_ops_group2~0.base=0bv32, ~tegra_rtc_ops_group2~0.offset=0bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] ----- [2018-11-23 07:29:19,817 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-11-23 07:29:19,818 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,818 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,818 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,819 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-11-23 07:29:19,819 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-11-23 07:29:19,819 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-11-23 07:29:19,819 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-11-23 07:29:19,819 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-11-23 07:29:19,820 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,820 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,820 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,820 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-11-23 07:29:19,820 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-11-23 07:29:19,821 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-23 07:29:19,823 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,823 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,824 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,825 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,826 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,826 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,827 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,828 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,829 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,830 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,831 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,831 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,837 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,837 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,837 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,838 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,838 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,838 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,839 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,840 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,840 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,840 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,840 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,841 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,841 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,842 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,842 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,843 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,844 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,844 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,844 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,845 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,845 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,846 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,846 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,846 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,847 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,847 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,848 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,848 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,849 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,850 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,850 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,851 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,851 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,851 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,852 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,852 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,852 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,852 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,853 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,853 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,854 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,854 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,854 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,855 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,855 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,855 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,855 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,856 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,856 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,857 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,857 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,857 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,858 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,858 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,858 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,858 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,858 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,859 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,860 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,861 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,862 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-23 07:29:19,862 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,862 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,863 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,863 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,864 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,887 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,887 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,887 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,888 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,888 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,889 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,889 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,890 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,890 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,891 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,891 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,892 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,892 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,893 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,893 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,894 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,894 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,894 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,895 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,895 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,895 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,896 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-23 07:29:19,896 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2529] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, memset((void *)(& ldvarg2), 0, 4U)={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2565] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2569] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2479] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] EXPR info->rtc_base [L1867] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={67108865:-13}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}, tmp___1=0] [L2016] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L2017] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] ----- [2018-11-23 07:29:21,150 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 07:29:21 BoogieIcfgContainer [2018-11-23 07:29:21,150 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 07:29:21,150 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 07:29:21,150 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 07:29:21,151 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 07:29:21,151 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:29:01" (3/4) ... [2018-11-23 07:29:21,154 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-23 07:29:21,154 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 07:29:21,155 INFO L168 Benchmark]: Toolchain (without parser) took 23585.47 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 385.4 MB). Free memory was 944.4 MB in the beginning and 894.7 MB in the end (delta: 49.7 MB). Peak memory consumption was 435.0 MB. Max. memory is 11.5 GB. [2018-11-23 07:29:21,156 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:29:21,157 INFO L168 Benchmark]: CACSL2BoogieTranslator took 806.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 151.5 MB). Free memory was 944.4 MB in the beginning and 1.1 GB in the end (delta: -160.4 MB). Peak memory consumption was 68.0 MB. Max. memory is 11.5 GB. [2018-11-23 07:29:21,157 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.69 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:29:21,157 INFO L168 Benchmark]: Boogie Preprocessor took 63.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-11-23 07:29:21,158 INFO L168 Benchmark]: RCFGBuilder took 2983.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 975.3 MB in the end (delta: 122.5 MB). Peak memory consumption was 122.5 MB. Max. memory is 11.5 GB. [2018-11-23 07:29:21,158 INFO L168 Benchmark]: TraceAbstraction took 19687.25 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 233.8 MB). Free memory was 975.3 MB in the beginning and 894.7 MB in the end (delta: 80.7 MB). Peak memory consumption was 314.5 MB. Max. memory is 11.5 GB. [2018-11-23 07:29:21,159 INFO L168 Benchmark]: Witness Printer took 4.18 ms. Allocated memory is still 1.4 GB. Free memory is still 894.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:29:21,161 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 806.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 151.5 MB). Free memory was 944.4 MB in the beginning and 1.1 GB in the end (delta: -160.4 MB). Peak memory consumption was 68.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.69 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 63.25 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2983.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 975.3 MB in the end (delta: 122.5 MB). Peak memory consumption was 122.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19687.25 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 233.8 MB). Free memory was 975.3 MB in the beginning and 894.7 MB in the end (delta: 80.7 MB). Peak memory consumption was 314.5 MB. Max. memory is 11.5 GB. * Witness Printer took 4.18 ms. Allocated memory is still 1.4 GB. Free memory is still 894.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1684]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2323. Possible FailurePath: [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2529] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, memset((void *)(& ldvarg2), 0, 4U)={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2565] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2569] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2479] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] EXPR info->rtc_base [L1867] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={67108865:-13}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}, tmp___1=0] [L2016] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L2017] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 363 locations, 1 error locations. UNSAFE Result, 19.6s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 7.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4530 SDtfs, 4960 SDslu, 11293 SDs, 0 SdLazy, 4757 SolverSat, 651 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1771 GetRequests, 1635 SyntacticMatches, 9 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1116occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 1437 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 2.7s SatisfiabilityAnalysisTime, 2.0s InterpolantComputationTime, 1203 NumberOfCodeBlocks, 1203 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 1702 ConstructedInterpolants, 0 QuantifiedInterpolants, 231860 SizeOfPredicates, 60 NumberOfNonLiveVariables, 8429 ConjunctsInSsa, 138 ConjunctsInUnsatCore, 27 InterpolantComputations, 10 PerfectInterpolantSequences, 147/227 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...