./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix033_pso.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix033_pso.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5225c06c798b79433014bd7aed4e3fee4a02538 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 07:19:32,544 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 07:19:32,545 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 07:19:32,554 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 07:19:32,554 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 07:19:32,554 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 07:19:32,555 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 07:19:32,556 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 07:19:32,557 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 07:19:32,557 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 07:19:32,558 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 07:19:32,558 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 07:19:32,559 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 07:19:32,559 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 07:19:32,560 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 07:19:32,561 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 07:19:32,561 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 07:19:32,562 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 07:19:32,564 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 07:19:32,565 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 07:19:32,565 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 07:19:32,566 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 07:19:32,568 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 07:19:32,568 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 07:19:32,568 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 07:19:32,569 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 07:19:32,569 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 07:19:32,570 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 07:19:32,570 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 07:19:32,571 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 07:19:32,571 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 07:19:32,572 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 07:19:32,572 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 07:19:32,572 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 07:19:32,573 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 07:19:32,573 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 07:19:32,573 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-23 07:19:32,583 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 07:19:32,583 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 07:19:32,584 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 07:19:32,584 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 07:19:32,584 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 07:19:32,584 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 07:19:32,584 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 07:19:32,585 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 07:19:32,586 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 07:19:32,586 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 07:19:32,586 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 07:19:32,586 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 07:19:32,586 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 07:19:32,587 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 07:19:32,588 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:19:32,588 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 07:19:32,588 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 07:19:32,589 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 07:19:32,589 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 07:19:32,589 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 07:19:32,589 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 07:19:32,589 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5225c06c798b79433014bd7aed4e3fee4a02538 [2018-11-23 07:19:32,610 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 07:19:32,618 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 07:19:32,620 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 07:19:32,620 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 07:19:32,621 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 07:19:32,621 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/../../sv-benchmarks/c/pthread-wmm/mix033_pso.opt_false-unreach-call.i [2018-11-23 07:19:32,655 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/data/b100ea832/c1ccc9a6fdd949d5af9666a1e2676b37/FLAGc6d91e42b [2018-11-23 07:19:33,101 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 07:19:33,102 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/sv-benchmarks/c/pthread-wmm/mix033_pso.opt_false-unreach-call.i [2018-11-23 07:19:33,112 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/data/b100ea832/c1ccc9a6fdd949d5af9666a1e2676b37/FLAGc6d91e42b [2018-11-23 07:19:33,121 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/data/b100ea832/c1ccc9a6fdd949d5af9666a1e2676b37 [2018-11-23 07:19:33,123 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 07:19:33,124 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 07:19:33,124 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 07:19:33,124 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 07:19:33,126 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 07:19:33,126 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,128 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e1fb88e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33, skipping insertion in model container [2018-11-23 07:19:33,128 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,134 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 07:19:33,163 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 07:19:33,395 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:19:33,403 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 07:19:33,491 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:19:33,528 INFO L195 MainTranslator]: Completed translation [2018-11-23 07:19:33,528 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33 WrapperNode [2018-11-23 07:19:33,528 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 07:19:33,529 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 07:19:33,529 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 07:19:33,529 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 07:19:33,534 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,549 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,571 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 07:19:33,571 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 07:19:33,571 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 07:19:33,572 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 07:19:33,578 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,578 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,582 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,582 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,590 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,593 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,595 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... [2018-11-23 07:19:33,598 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 07:19:33,599 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 07:19:33,599 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 07:19:33,599 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 07:19:33,600 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:19:33,642 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 07:19:33,642 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 07:19:33,643 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 07:19:33,643 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 07:19:33,643 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 07:19:33,643 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 07:19:33,643 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 07:19:33,643 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 07:19:33,643 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2018-11-23 07:19:33,643 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2018-11-23 07:19:33,644 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 07:19:33,644 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 07:19:33,644 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 07:19:33,645 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 07:19:34,113 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 07:19:34,114 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 07:19:34,114 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:19:34 BoogieIcfgContainer [2018-11-23 07:19:34,114 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 07:19:34,115 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 07:19:34,115 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 07:19:34,116 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 07:19:34,117 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 07:19:33" (1/3) ... [2018-11-23 07:19:34,117 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ea48122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:19:34, skipping insertion in model container [2018-11-23 07:19:34,117 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:19:33" (2/3) ... [2018-11-23 07:19:34,117 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ea48122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:19:34, skipping insertion in model container [2018-11-23 07:19:34,117 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:19:34" (3/3) ... [2018-11-23 07:19:34,119 INFO L112 eAbstractionObserver]: Analyzing ICFG mix033_pso.opt_false-unreach-call.i [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe Thread1_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,145 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P0_#t~nondet3.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe Thread2_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,146 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe Thread2_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet4.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet5.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,147 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,148 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,149 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,150 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,151 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,152 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,153 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,154 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread2_P1_#t~nondet27.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,155 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe Thread0_P2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,156 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,157 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,157 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,157 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,157 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,157 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,158 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,159 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,159 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,159 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,159 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,159 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,160 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P2_#t~nondet34.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:19:34,181 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 07:19:34,182 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 07:19:34,187 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 07:19:34,197 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 07:19:34,215 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 07:19:34,215 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 07:19:34,215 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 07:19:34,216 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 07:19:34,216 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 07:19:34,216 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 07:19:34,216 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 07:19:34,216 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 07:19:34,225 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 148places, 179 transitions [2018-11-23 07:19:57,038 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 149047 states. [2018-11-23 07:19:57,040 INFO L276 IsEmpty]: Start isEmpty. Operand 149047 states. [2018-11-23 07:19:57,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 07:19:57,049 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:19:57,050 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:19:57,051 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:19:57,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:19:57,056 INFO L82 PathProgramCache]: Analyzing trace with hash -552567723, now seen corresponding path program 1 times [2018-11-23 07:19:57,057 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:19:57,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:19:57,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:19:57,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:19:57,105 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:19:57,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:19:57,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:19:57,257 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:19:57,257 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 07:19:57,257 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:19:57,261 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 07:19:57,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 07:19:57,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:19:57,271 INFO L87 Difference]: Start difference. First operand 149047 states. Second operand 4 states. [2018-11-23 07:20:00,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:00,913 INFO L93 Difference]: Finished difference Result 257067 states and 1188606 transitions. [2018-11-23 07:20:00,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 07:20:00,915 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 48 [2018-11-23 07:20:00,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:01,617 INFO L225 Difference]: With dead ends: 257067 [2018-11-23 07:20:01,617 INFO L226 Difference]: Without dead ends: 174817 [2018-11-23 07:20:01,618 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:20:02,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174817 states. [2018-11-23 07:20:04,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174817 to 110557. [2018-11-23 07:20:04,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110557 states. [2018-11-23 07:20:05,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110557 states to 110557 states and 511488 transitions. [2018-11-23 07:20:05,354 INFO L78 Accepts]: Start accepts. Automaton has 110557 states and 511488 transitions. Word has length 48 [2018-11-23 07:20:05,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:05,355 INFO L480 AbstractCegarLoop]: Abstraction has 110557 states and 511488 transitions. [2018-11-23 07:20:05,355 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 07:20:05,355 INFO L276 IsEmpty]: Start isEmpty. Operand 110557 states and 511488 transitions. [2018-11-23 07:20:05,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 07:20:05,371 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:05,371 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:05,371 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:05,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:05,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1274372901, now seen corresponding path program 1 times [2018-11-23 07:20:05,372 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:05,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:05,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:05,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:05,376 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:05,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:05,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:05,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:05,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:20:05,449 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:05,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:20:05,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:20:05,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:05,451 INFO L87 Difference]: Start difference. First operand 110557 states and 511488 transitions. Second operand 3 states. [2018-11-23 07:20:06,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:06,164 INFO L93 Difference]: Finished difference Result 110557 states and 511383 transitions. [2018-11-23 07:20:06,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:20:06,164 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2018-11-23 07:20:06,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:06,465 INFO L225 Difference]: With dead ends: 110557 [2018-11-23 07:20:06,465 INFO L226 Difference]: Without dead ends: 110557 [2018-11-23 07:20:06,466 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:10,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110557 states. [2018-11-23 07:20:11,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110557 to 110557. [2018-11-23 07:20:11,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110557 states. [2018-11-23 07:20:11,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110557 states to 110557 states and 511383 transitions. [2018-11-23 07:20:11,855 INFO L78 Accepts]: Start accepts. Automaton has 110557 states and 511383 transitions. Word has length 56 [2018-11-23 07:20:11,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:11,856 INFO L480 AbstractCegarLoop]: Abstraction has 110557 states and 511383 transitions. [2018-11-23 07:20:11,856 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:20:11,856 INFO L276 IsEmpty]: Start isEmpty. Operand 110557 states and 511383 transitions. [2018-11-23 07:20:11,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 07:20:11,867 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:11,868 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:11,868 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:11,868 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:11,868 INFO L82 PathProgramCache]: Analyzing trace with hash 468437434, now seen corresponding path program 1 times [2018-11-23 07:20:11,868 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:11,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:11,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:11,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:11,873 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:11,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:11,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:11,939 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:11,939 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 07:20:11,939 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:11,940 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 07:20:11,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 07:20:11,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:20:11,942 INFO L87 Difference]: Start difference. First operand 110557 states and 511383 transitions. Second operand 4 states. [2018-11-23 07:20:12,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:12,438 INFO L93 Difference]: Finished difference Result 99455 states and 448608 transitions. [2018-11-23 07:20:12,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 07:20:12,439 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 56 [2018-11-23 07:20:12,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:13,247 INFO L225 Difference]: With dead ends: 99455 [2018-11-23 07:20:13,248 INFO L226 Difference]: Without dead ends: 95225 [2018-11-23 07:20:13,248 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:13,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95225 states. [2018-11-23 07:20:14,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95225 to 95225. [2018-11-23 07:20:14,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95225 states. [2018-11-23 07:20:15,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95225 states to 95225 states and 432992 transitions. [2018-11-23 07:20:15,046 INFO L78 Accepts]: Start accepts. Automaton has 95225 states and 432992 transitions. Word has length 56 [2018-11-23 07:20:15,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:15,046 INFO L480 AbstractCegarLoop]: Abstraction has 95225 states and 432992 transitions. [2018-11-23 07:20:15,046 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 07:20:15,047 INFO L276 IsEmpty]: Start isEmpty. Operand 95225 states and 432992 transitions. [2018-11-23 07:20:15,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 07:20:15,053 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:15,054 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:15,054 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:15,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:15,054 INFO L82 PathProgramCache]: Analyzing trace with hash -1865372316, now seen corresponding path program 1 times [2018-11-23 07:20:15,054 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:15,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:15,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:15,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:15,057 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:15,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:15,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:15,134 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:15,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:20:15,134 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:15,134 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:20:15,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:20:15,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:15,135 INFO L87 Difference]: Start difference. First operand 95225 states and 432992 transitions. Second operand 5 states. [2018-11-23 07:20:15,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:15,289 INFO L93 Difference]: Finished difference Result 30969 states and 124172 transitions. [2018-11-23 07:20:15,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:20:15,290 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 07:20:15,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:15,357 INFO L225 Difference]: With dead ends: 30969 [2018-11-23 07:20:15,357 INFO L226 Difference]: Without dead ends: 27341 [2018-11-23 07:20:15,357 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:15,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27341 states. [2018-11-23 07:20:15,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27341 to 26881. [2018-11-23 07:20:15,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26881 states. [2018-11-23 07:20:16,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26881 states to 26881 states and 107654 transitions. [2018-11-23 07:20:16,466 INFO L78 Accepts]: Start accepts. Automaton has 26881 states and 107654 transitions. Word has length 57 [2018-11-23 07:20:16,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:16,466 INFO L480 AbstractCegarLoop]: Abstraction has 26881 states and 107654 transitions. [2018-11-23 07:20:16,466 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:20:16,466 INFO L276 IsEmpty]: Start isEmpty. Operand 26881 states and 107654 transitions. [2018-11-23 07:20:16,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 07:20:16,468 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:16,468 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:16,468 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:16,469 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:16,469 INFO L82 PathProgramCache]: Analyzing trace with hash 1683293826, now seen corresponding path program 1 times [2018-11-23 07:20:16,469 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:16,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:16,470 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:16,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:16,471 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:16,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:16,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:16,540 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:16,540 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:16,541 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:16,541 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:16,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:16,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:16,541 INFO L87 Difference]: Start difference. First operand 26881 states and 107654 transitions. Second operand 6 states. [2018-11-23 07:20:16,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:16,862 INFO L93 Difference]: Finished difference Result 37433 states and 146191 transitions. [2018-11-23 07:20:16,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:20:16,862 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 57 [2018-11-23 07:20:16,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:16,929 INFO L225 Difference]: With dead ends: 37433 [2018-11-23 07:20:16,929 INFO L226 Difference]: Without dead ends: 37058 [2018-11-23 07:20:16,930 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2018-11-23 07:20:17,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37058 states. [2018-11-23 07:20:17,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37058 to 35274. [2018-11-23 07:20:17,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35274 states. [2018-11-23 07:20:17,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35274 states to 35274 states and 138749 transitions. [2018-11-23 07:20:17,435 INFO L78 Accepts]: Start accepts. Automaton has 35274 states and 138749 transitions. Word has length 57 [2018-11-23 07:20:17,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:17,435 INFO L480 AbstractCegarLoop]: Abstraction has 35274 states and 138749 transitions. [2018-11-23 07:20:17,435 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:17,435 INFO L276 IsEmpty]: Start isEmpty. Operand 35274 states and 138749 transitions. [2018-11-23 07:20:17,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-11-23 07:20:17,438 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:17,438 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:17,439 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:17,439 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:17,439 INFO L82 PathProgramCache]: Analyzing trace with hash -674729880, now seen corresponding path program 1 times [2018-11-23 07:20:17,439 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:17,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:17,440 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:17,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:17,441 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:17,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:17,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:17,466 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:17,466 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:20:17,466 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:17,467 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:20:17,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:20:17,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:17,467 INFO L87 Difference]: Start difference. First operand 35274 states and 138749 transitions. Second operand 3 states. [2018-11-23 07:20:17,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:17,652 INFO L93 Difference]: Finished difference Result 46814 states and 182041 transitions. [2018-11-23 07:20:17,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:20:17,652 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2018-11-23 07:20:17,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:17,732 INFO L225 Difference]: With dead ends: 46814 [2018-11-23 07:20:17,732 INFO L226 Difference]: Without dead ends: 46794 [2018-11-23 07:20:17,733 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:17,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46794 states. [2018-11-23 07:20:18,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46794 to 36256. [2018-11-23 07:20:18,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36256 states. [2018-11-23 07:20:18,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36256 states to 36256 states and 141456 transitions. [2018-11-23 07:20:18,294 INFO L78 Accepts]: Start accepts. Automaton has 36256 states and 141456 transitions. Word has length 59 [2018-11-23 07:20:18,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:18,294 INFO L480 AbstractCegarLoop]: Abstraction has 36256 states and 141456 transitions. [2018-11-23 07:20:18,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:20:18,294 INFO L276 IsEmpty]: Start isEmpty. Operand 36256 states and 141456 transitions. [2018-11-23 07:20:18,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-11-23 07:20:18,298 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:18,298 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:18,298 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:18,298 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:18,298 INFO L82 PathProgramCache]: Analyzing trace with hash 2071932979, now seen corresponding path program 1 times [2018-11-23 07:20:18,298 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:18,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:18,300 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:18,300 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:18,300 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:18,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:18,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:18,372 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:18,372 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:18,372 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:18,372 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:18,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:18,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:18,373 INFO L87 Difference]: Start difference. First operand 36256 states and 141456 transitions. Second operand 6 states. [2018-11-23 07:20:18,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:18,801 INFO L93 Difference]: Finished difference Result 50348 states and 193878 transitions. [2018-11-23 07:20:18,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 07:20:18,801 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 63 [2018-11-23 07:20:18,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:18,901 INFO L225 Difference]: With dead ends: 50348 [2018-11-23 07:20:18,901 INFO L226 Difference]: Without dead ends: 49863 [2018-11-23 07:20:18,902 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-11-23 07:20:19,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49863 states. [2018-11-23 07:20:19,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49863 to 39290. [2018-11-23 07:20:19,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39290 states. [2018-11-23 07:20:19,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39290 states to 39290 states and 153277 transitions. [2018-11-23 07:20:19,594 INFO L78 Accepts]: Start accepts. Automaton has 39290 states and 153277 transitions. Word has length 63 [2018-11-23 07:20:19,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:19,595 INFO L480 AbstractCegarLoop]: Abstraction has 39290 states and 153277 transitions. [2018-11-23 07:20:19,595 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:19,595 INFO L276 IsEmpty]: Start isEmpty. Operand 39290 states and 153277 transitions. [2018-11-23 07:20:19,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-23 07:20:19,614 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:19,614 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:19,615 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:19,615 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:19,615 INFO L82 PathProgramCache]: Analyzing trace with hash -276513334, now seen corresponding path program 1 times [2018-11-23 07:20:19,615 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:19,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:19,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:19,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:19,617 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:19,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:19,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:19,680 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:19,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 07:20:19,681 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:19,681 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 07:20:19,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 07:20:19,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:20:19,682 INFO L87 Difference]: Start difference. First operand 39290 states and 153277 transitions. Second operand 4 states. [2018-11-23 07:20:20,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:20,148 INFO L93 Difference]: Finished difference Result 46153 states and 179280 transitions. [2018-11-23 07:20:20,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 07:20:20,149 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 74 [2018-11-23 07:20:20,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:20,236 INFO L225 Difference]: With dead ends: 46153 [2018-11-23 07:20:20,236 INFO L226 Difference]: Without dead ends: 46153 [2018-11-23 07:20:20,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:20,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46153 states. [2018-11-23 07:20:20,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46153 to 42185. [2018-11-23 07:20:20,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42185 states. [2018-11-23 07:20:20,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42185 states to 42185 states and 164112 transitions. [2018-11-23 07:20:20,883 INFO L78 Accepts]: Start accepts. Automaton has 42185 states and 164112 transitions. Word has length 74 [2018-11-23 07:20:20,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:20,883 INFO L480 AbstractCegarLoop]: Abstraction has 42185 states and 164112 transitions. [2018-11-23 07:20:20,883 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 07:20:20,883 INFO L276 IsEmpty]: Start isEmpty. Operand 42185 states and 164112 transitions. [2018-11-23 07:20:20,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-23 07:20:20,903 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:20,903 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:20,904 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:20,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:20,904 INFO L82 PathProgramCache]: Analyzing trace with hash 1466297001, now seen corresponding path program 1 times [2018-11-23 07:20:20,904 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:20,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:20,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:20,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:20,906 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:20,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:20,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:20,975 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:20,976 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:20,976 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:20,976 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:20,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:20,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:20,976 INFO L87 Difference]: Start difference. First operand 42185 states and 164112 transitions. Second operand 6 states. [2018-11-23 07:20:21,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:21,630 INFO L93 Difference]: Finished difference Result 91408 states and 351791 transitions. [2018-11-23 07:20:21,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 07:20:21,631 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2018-11-23 07:20:21,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:21,822 INFO L225 Difference]: With dead ends: 91408 [2018-11-23 07:20:21,823 INFO L226 Difference]: Without dead ends: 91088 [2018-11-23 07:20:21,823 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-11-23 07:20:22,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91088 states. [2018-11-23 07:20:22,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91088 to 55498. [2018-11-23 07:20:22,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55498 states. [2018-11-23 07:20:22,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55498 states to 55498 states and 213500 transitions. [2018-11-23 07:20:22,931 INFO L78 Accepts]: Start accepts. Automaton has 55498 states and 213500 transitions. Word has length 74 [2018-11-23 07:20:22,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:22,931 INFO L480 AbstractCegarLoop]: Abstraction has 55498 states and 213500 transitions. [2018-11-23 07:20:22,931 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:22,931 INFO L276 IsEmpty]: Start isEmpty. Operand 55498 states and 213500 transitions. [2018-11-23 07:20:22,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 07:20:22,961 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:22,961 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:22,961 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:22,961 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:22,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1987377366, now seen corresponding path program 1 times [2018-11-23 07:20:22,962 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:22,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:22,963 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:22,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:22,963 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:22,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:23,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:23,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:23,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 07:20:23,035 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:23,035 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 07:20:23,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 07:20:23,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:20:23,035 INFO L87 Difference]: Start difference. First operand 55498 states and 213500 transitions. Second operand 4 states. [2018-11-23 07:20:23,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:23,445 INFO L93 Difference]: Finished difference Result 70629 states and 268392 transitions. [2018-11-23 07:20:23,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 07:20:23,446 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 76 [2018-11-23 07:20:23,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:23,588 INFO L225 Difference]: With dead ends: 70629 [2018-11-23 07:20:23,588 INFO L226 Difference]: Without dead ends: 70629 [2018-11-23 07:20:23,588 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 07:20:23,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70629 states. [2018-11-23 07:20:24,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70629 to 63993. [2018-11-23 07:20:24,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63993 states. [2018-11-23 07:20:24,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63993 states to 63993 states and 243820 transitions. [2018-11-23 07:20:24,691 INFO L78 Accepts]: Start accepts. Automaton has 63993 states and 243820 transitions. Word has length 76 [2018-11-23 07:20:24,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:24,691 INFO L480 AbstractCegarLoop]: Abstraction has 63993 states and 243820 transitions. [2018-11-23 07:20:24,691 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 07:20:24,691 INFO L276 IsEmpty]: Start isEmpty. Operand 63993 states and 243820 transitions. [2018-11-23 07:20:24,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 07:20:24,724 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:24,724 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:24,724 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:24,724 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:24,725 INFO L82 PathProgramCache]: Analyzing trace with hash -89831977, now seen corresponding path program 1 times [2018-11-23 07:20:24,725 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:24,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:24,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:24,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:24,726 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:24,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:24,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:24,752 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:24,752 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 07:20:24,752 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:24,752 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 07:20:24,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 07:20:24,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:24,754 INFO L87 Difference]: Start difference. First operand 63993 states and 243820 transitions. Second operand 3 states. [2018-11-23 07:20:25,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:25,127 INFO L93 Difference]: Finished difference Result 66627 states and 253017 transitions. [2018-11-23 07:20:25,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 07:20:25,128 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2018-11-23 07:20:25,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:25,263 INFO L225 Difference]: With dead ends: 66627 [2018-11-23 07:20:25,263 INFO L226 Difference]: Without dead ends: 66627 [2018-11-23 07:20:25,264 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 07:20:25,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66627 states. [2018-11-23 07:20:26,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66627 to 65439. [2018-11-23 07:20:26,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65439 states. [2018-11-23 07:20:26,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65439 states to 65439 states and 248840 transitions. [2018-11-23 07:20:26,291 INFO L78 Accepts]: Start accepts. Automaton has 65439 states and 248840 transitions. Word has length 76 [2018-11-23 07:20:26,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:26,291 INFO L480 AbstractCegarLoop]: Abstraction has 65439 states and 248840 transitions. [2018-11-23 07:20:26,291 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 07:20:26,291 INFO L276 IsEmpty]: Start isEmpty. Operand 65439 states and 248840 transitions. [2018-11-23 07:20:26,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 07:20:26,343 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:26,343 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:26,343 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:26,343 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:26,343 INFO L82 PathProgramCache]: Analyzing trace with hash 2086484495, now seen corresponding path program 1 times [2018-11-23 07:20:26,343 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:26,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:26,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:26,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:26,345 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:26,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:26,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:26,416 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:26,416 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:26,416 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:26,416 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:26,416 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:26,416 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:26,417 INFO L87 Difference]: Start difference. First operand 65439 states and 248840 transitions. Second operand 6 states. [2018-11-23 07:20:27,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:27,174 INFO L93 Difference]: Finished difference Result 79698 states and 299735 transitions. [2018-11-23 07:20:27,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:20:27,175 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-23 07:20:27,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:27,340 INFO L225 Difference]: With dead ends: 79698 [2018-11-23 07:20:27,340 INFO L226 Difference]: Without dead ends: 79698 [2018-11-23 07:20:27,340 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:27,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79698 states. [2018-11-23 07:20:28,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79698 to 75406. [2018-11-23 07:20:28,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75406 states. [2018-11-23 07:20:28,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75406 states to 75406 states and 284925 transitions. [2018-11-23 07:20:28,672 INFO L78 Accepts]: Start accepts. Automaton has 75406 states and 284925 transitions. Word has length 78 [2018-11-23 07:20:28,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:28,672 INFO L480 AbstractCegarLoop]: Abstraction has 75406 states and 284925 transitions. [2018-11-23 07:20:28,672 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:28,672 INFO L276 IsEmpty]: Start isEmpty. Operand 75406 states and 284925 transitions. [2018-11-23 07:20:28,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 07:20:28,718 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:28,718 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:28,718 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:28,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:28,718 INFO L82 PathProgramCache]: Analyzing trace with hash 9275152, now seen corresponding path program 1 times [2018-11-23 07:20:28,719 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:28,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:28,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:28,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:28,720 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:28,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:28,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:28,787 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:28,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:28,787 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:28,787 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:28,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:28,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:28,788 INFO L87 Difference]: Start difference. First operand 75406 states and 284925 transitions. Second operand 6 states. [2018-11-23 07:20:29,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:29,277 INFO L93 Difference]: Finished difference Result 88588 states and 326142 transitions. [2018-11-23 07:20:29,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 07:20:29,278 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-23 07:20:29,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:29,447 INFO L225 Difference]: With dead ends: 88588 [2018-11-23 07:20:29,447 INFO L226 Difference]: Without dead ends: 88588 [2018-11-23 07:20:29,448 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 07:20:29,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88588 states. [2018-11-23 07:20:30,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88588 to 76931. [2018-11-23 07:20:30,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76931 states. [2018-11-23 07:20:30,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76931 states to 76931 states and 285924 transitions. [2018-11-23 07:20:30,600 INFO L78 Accepts]: Start accepts. Automaton has 76931 states and 285924 transitions. Word has length 78 [2018-11-23 07:20:30,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:30,600 INFO L480 AbstractCegarLoop]: Abstraction has 76931 states and 285924 transitions. [2018-11-23 07:20:30,600 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:30,600 INFO L276 IsEmpty]: Start isEmpty. Operand 76931 states and 285924 transitions. [2018-11-23 07:20:30,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 07:20:30,644 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:30,644 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:30,644 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:30,644 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:30,644 INFO L82 PathProgramCache]: Analyzing trace with hash 220626065, now seen corresponding path program 1 times [2018-11-23 07:20:30,644 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:30,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:30,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:30,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:30,646 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:30,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:30,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:30,724 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:30,724 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:20:30,724 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:30,724 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:20:30,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:20:30,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:30,725 INFO L87 Difference]: Start difference. First operand 76931 states and 285924 transitions. Second operand 5 states. [2018-11-23 07:20:31,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:31,396 INFO L93 Difference]: Finished difference Result 97024 states and 358812 transitions. [2018-11-23 07:20:31,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:20:31,396 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 78 [2018-11-23 07:20:31,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:31,563 INFO L225 Difference]: With dead ends: 97024 [2018-11-23 07:20:31,563 INFO L226 Difference]: Without dead ends: 97024 [2018-11-23 07:20:31,563 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:31,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97024 states. [2018-11-23 07:20:32,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97024 to 82886. [2018-11-23 07:20:32,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82886 states. [2018-11-23 07:20:32,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82886 states to 82886 states and 305942 transitions. [2018-11-23 07:20:32,762 INFO L78 Accepts]: Start accepts. Automaton has 82886 states and 305942 transitions. Word has length 78 [2018-11-23 07:20:32,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:32,762 INFO L480 AbstractCegarLoop]: Abstraction has 82886 states and 305942 transitions. [2018-11-23 07:20:32,762 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:20:32,762 INFO L276 IsEmpty]: Start isEmpty. Operand 82886 states and 305942 transitions. [2018-11-23 07:20:32,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 07:20:32,817 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:32,817 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:32,818 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:32,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:32,818 INFO L82 PathProgramCache]: Analyzing trace with hash -289908112, now seen corresponding path program 1 times [2018-11-23 07:20:32,818 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:32,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:32,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:32,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:32,819 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:32,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:32,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:32,907 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:32,907 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:20:32,907 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:32,908 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:20:32,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:20:32,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:32,908 INFO L87 Difference]: Start difference. First operand 82886 states and 305942 transitions. Second operand 5 states. [2018-11-23 07:20:33,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:33,671 INFO L93 Difference]: Finished difference Result 112009 states and 412190 transitions. [2018-11-23 07:20:33,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:20:33,672 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 78 [2018-11-23 07:20:33,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:33,904 INFO L225 Difference]: With dead ends: 112009 [2018-11-23 07:20:33,904 INFO L226 Difference]: Without dead ends: 112009 [2018-11-23 07:20:33,905 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:20:34,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112009 states. [2018-11-23 07:20:35,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112009 to 87819. [2018-11-23 07:20:35,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87819 states. [2018-11-23 07:20:35,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87819 states to 87819 states and 324136 transitions. [2018-11-23 07:20:35,613 INFO L78 Accepts]: Start accepts. Automaton has 87819 states and 324136 transitions. Word has length 78 [2018-11-23 07:20:35,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:35,613 INFO L480 AbstractCegarLoop]: Abstraction has 87819 states and 324136 transitions. [2018-11-23 07:20:35,613 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:20:35,614 INFO L276 IsEmpty]: Start isEmpty. Operand 87819 states and 324136 transitions. [2018-11-23 07:20:35,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-11-23 07:20:35,663 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:35,663 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:35,663 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:35,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:35,664 INFO L82 PathProgramCache]: Analyzing trace with hash -2097362575, now seen corresponding path program 1 times [2018-11-23 07:20:35,664 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:35,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:35,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:35,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:35,665 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:35,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:35,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:35,728 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:35,728 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:35,728 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:35,728 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:35,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:35,728 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:35,729 INFO L87 Difference]: Start difference. First operand 87819 states and 324136 transitions. Second operand 6 states. [2018-11-23 07:20:35,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:35,849 INFO L93 Difference]: Finished difference Result 31979 states and 101192 transitions. [2018-11-23 07:20:35,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:20:35,850 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 78 [2018-11-23 07:20:35,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:35,882 INFO L225 Difference]: With dead ends: 31979 [2018-11-23 07:20:35,882 INFO L226 Difference]: Without dead ends: 25698 [2018-11-23 07:20:35,882 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-11-23 07:20:35,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25698 states. [2018-11-23 07:20:36,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25698 to 22278. [2018-11-23 07:20:36,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22278 states. [2018-11-23 07:20:36,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22278 states to 22278 states and 69699 transitions. [2018-11-23 07:20:36,131 INFO L78 Accepts]: Start accepts. Automaton has 22278 states and 69699 transitions. Word has length 78 [2018-11-23 07:20:36,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:36,131 INFO L480 AbstractCegarLoop]: Abstraction has 22278 states and 69699 transitions. [2018-11-23 07:20:36,132 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:36,132 INFO L276 IsEmpty]: Start isEmpty. Operand 22278 states and 69699 transitions. [2018-11-23 07:20:36,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 07:20:36,152 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:36,152 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:36,153 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:36,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:36,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1243988963, now seen corresponding path program 1 times [2018-11-23 07:20:36,153 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:36,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:36,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:36,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:36,154 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:36,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:36,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:36,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:36,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 07:20:36,250 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:36,250 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 07:20:36,250 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 07:20:36,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:36,251 INFO L87 Difference]: Start difference. First operand 22278 states and 69699 transitions. Second operand 7 states. [2018-11-23 07:20:36,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:36,722 INFO L93 Difference]: Finished difference Result 28056 states and 87492 transitions. [2018-11-23 07:20:36,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 07:20:36,723 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 93 [2018-11-23 07:20:36,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:36,759 INFO L225 Difference]: With dead ends: 28056 [2018-11-23 07:20:36,759 INFO L226 Difference]: Without dead ends: 28056 [2018-11-23 07:20:36,760 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:36,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28056 states. [2018-11-23 07:20:37,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28056 to 23028. [2018-11-23 07:20:37,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23028 states. [2018-11-23 07:20:37,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23028 states to 23028 states and 72249 transitions. [2018-11-23 07:20:37,081 INFO L78 Accepts]: Start accepts. Automaton has 23028 states and 72249 transitions. Word has length 93 [2018-11-23 07:20:37,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:37,081 INFO L480 AbstractCegarLoop]: Abstraction has 23028 states and 72249 transitions. [2018-11-23 07:20:37,081 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 07:20:37,081 INFO L276 IsEmpty]: Start isEmpty. Operand 23028 states and 72249 transitions. [2018-11-23 07:20:37,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 07:20:37,110 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:37,110 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:37,110 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:37,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:37,110 INFO L82 PathProgramCache]: Analyzing trace with hash -1996886328, now seen corresponding path program 1 times [2018-11-23 07:20:37,110 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:37,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:37,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:37,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:37,113 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:37,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:37,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:37,188 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:37,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:20:37,188 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:37,188 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:20:37,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:20:37,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:20:37,189 INFO L87 Difference]: Start difference. First operand 23028 states and 72249 transitions. Second operand 5 states. [2018-11-23 07:20:37,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:37,434 INFO L93 Difference]: Finished difference Result 26662 states and 82783 transitions. [2018-11-23 07:20:37,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:20:37,435 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 93 [2018-11-23 07:20:37,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:37,467 INFO L225 Difference]: With dead ends: 26662 [2018-11-23 07:20:37,468 INFO L226 Difference]: Without dead ends: 26492 [2018-11-23 07:20:37,468 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:20:37,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26492 states. [2018-11-23 07:20:37,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26492 to 23808. [2018-11-23 07:20:37,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23808 states. [2018-11-23 07:20:37,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23808 states to 23808 states and 74413 transitions. [2018-11-23 07:20:37,766 INFO L78 Accepts]: Start accepts. Automaton has 23808 states and 74413 transitions. Word has length 93 [2018-11-23 07:20:37,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:37,766 INFO L480 AbstractCegarLoop]: Abstraction has 23808 states and 74413 transitions. [2018-11-23 07:20:37,766 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:20:37,766 INFO L276 IsEmpty]: Start isEmpty. Operand 23808 states and 74413 transitions. [2018-11-23 07:20:37,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-11-23 07:20:37,791 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:37,791 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:37,791 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:37,792 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:37,792 INFO L82 PathProgramCache]: Analyzing trace with hash 240665687, now seen corresponding path program 2 times [2018-11-23 07:20:37,792 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:37,792 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:37,793 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:37,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:37,793 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:37,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:37,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:37,903 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:37,903 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:20:37,903 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:37,903 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:20:37,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:20:37,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:20:37,904 INFO L87 Difference]: Start difference. First operand 23808 states and 74413 transitions. Second operand 6 states. [2018-11-23 07:20:38,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:38,048 INFO L93 Difference]: Finished difference Result 23872 states and 74045 transitions. [2018-11-23 07:20:38,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:20:38,048 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 93 [2018-11-23 07:20:38,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:38,077 INFO L225 Difference]: With dead ends: 23872 [2018-11-23 07:20:38,077 INFO L226 Difference]: Without dead ends: 23872 [2018-11-23 07:20:38,077 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:38,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23872 states. [2018-11-23 07:20:38,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23872 to 16028. [2018-11-23 07:20:38,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16028 states. [2018-11-23 07:20:38,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16028 states to 16028 states and 50193 transitions. [2018-11-23 07:20:38,320 INFO L78 Accepts]: Start accepts. Automaton has 16028 states and 50193 transitions. Word has length 93 [2018-11-23 07:20:38,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:38,321 INFO L480 AbstractCegarLoop]: Abstraction has 16028 states and 50193 transitions. [2018-11-23 07:20:38,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:20:38,321 INFO L276 IsEmpty]: Start isEmpty. Operand 16028 states and 50193 transitions. [2018-11-23 07:20:38,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 07:20:38,337 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:38,337 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:38,337 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:38,338 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:38,338 INFO L82 PathProgramCache]: Analyzing trace with hash -1039801887, now seen corresponding path program 1 times [2018-11-23 07:20:38,338 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:38,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:38,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:20:38,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:38,339 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:38,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:38,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:38,444 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:38,444 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 07:20:38,444 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:38,444 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 07:20:38,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 07:20:38,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:20:38,445 INFO L87 Difference]: Start difference. First operand 16028 states and 50193 transitions. Second operand 8 states. [2018-11-23 07:20:38,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:38,706 INFO L93 Difference]: Finished difference Result 19085 states and 59341 transitions. [2018-11-23 07:20:38,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 07:20:38,707 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 95 [2018-11-23 07:20:38,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:38,729 INFO L225 Difference]: With dead ends: 19085 [2018-11-23 07:20:38,730 INFO L226 Difference]: Without dead ends: 19085 [2018-11-23 07:20:38,730 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=74, Invalid=166, Unknown=0, NotChecked=0, Total=240 [2018-11-23 07:20:38,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19085 states. [2018-11-23 07:20:38,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19085 to 18316. [2018-11-23 07:20:38,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18316 states. [2018-11-23 07:20:38,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18316 states to 18316 states and 57194 transitions. [2018-11-23 07:20:38,953 INFO L78 Accepts]: Start accepts. Automaton has 18316 states and 57194 transitions. Word has length 95 [2018-11-23 07:20:38,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:38,953 INFO L480 AbstractCegarLoop]: Abstraction has 18316 states and 57194 transitions. [2018-11-23 07:20:38,953 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 07:20:38,953 INFO L276 IsEmpty]: Start isEmpty. Operand 18316 states and 57194 transitions. [2018-11-23 07:20:38,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 07:20:38,972 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:38,972 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:38,972 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:38,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:38,973 INFO L82 PathProgramCache]: Analyzing trace with hash -152298206, now seen corresponding path program 1 times [2018-11-23 07:20:38,973 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:38,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:38,974 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:38,974 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:38,974 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:38,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:39,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:39,083 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:39,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 07:20:39,084 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:39,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 07:20:39,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 07:20:39,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 07:20:39,084 INFO L87 Difference]: Start difference. First operand 18316 states and 57194 transitions. Second operand 10 states. [2018-11-23 07:20:39,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:39,629 INFO L93 Difference]: Finished difference Result 34508 states and 107414 transitions. [2018-11-23 07:20:39,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 07:20:39,630 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 95 [2018-11-23 07:20:39,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:39,650 INFO L225 Difference]: With dead ends: 34508 [2018-11-23 07:20:39,650 INFO L226 Difference]: Without dead ends: 16352 [2018-11-23 07:20:39,650 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=171, Unknown=0, NotChecked=0, Total=240 [2018-11-23 07:20:39,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16352 states. [2018-11-23 07:20:39,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16352 to 16352. [2018-11-23 07:20:39,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16352 states. [2018-11-23 07:20:39,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16352 states to 16352 states and 50902 transitions. [2018-11-23 07:20:39,902 INFO L78 Accepts]: Start accepts. Automaton has 16352 states and 50902 transitions. Word has length 95 [2018-11-23 07:20:39,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:39,902 INFO L480 AbstractCegarLoop]: Abstraction has 16352 states and 50902 transitions. [2018-11-23 07:20:39,902 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 07:20:39,902 INFO L276 IsEmpty]: Start isEmpty. Operand 16352 states and 50902 transitions. [2018-11-23 07:20:39,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 07:20:39,918 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:39,918 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:39,918 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:39,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:39,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1733203426, now seen corresponding path program 2 times [2018-11-23 07:20:39,918 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:39,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:39,920 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:20:39,920 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:39,920 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:39,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:40,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:40,004 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:40,004 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 07:20:40,004 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:40,004 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 07:20:40,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 07:20:40,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 07:20:40,005 INFO L87 Difference]: Start difference. First operand 16352 states and 50902 transitions. Second operand 7 states. [2018-11-23 07:20:40,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:40,563 INFO L93 Difference]: Finished difference Result 28237 states and 87870 transitions. [2018-11-23 07:20:40,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:20:40,564 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-11-23 07:20:40,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:40,578 INFO L225 Difference]: With dead ends: 28237 [2018-11-23 07:20:40,578 INFO L226 Difference]: Without dead ends: 11338 [2018-11-23 07:20:40,578 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-11-23 07:20:40,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11338 states. [2018-11-23 07:20:40,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11338 to 11338. [2018-11-23 07:20:40,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11338 states. [2018-11-23 07:20:40,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11338 states to 11338 states and 35212 transitions. [2018-11-23 07:20:40,707 INFO L78 Accepts]: Start accepts. Automaton has 11338 states and 35212 transitions. Word has length 95 [2018-11-23 07:20:40,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:40,707 INFO L480 AbstractCegarLoop]: Abstraction has 11338 states and 35212 transitions. [2018-11-23 07:20:40,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 07:20:40,707 INFO L276 IsEmpty]: Start isEmpty. Operand 11338 states and 35212 transitions. [2018-11-23 07:20:40,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 07:20:40,718 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:40,718 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:40,718 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:40,718 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:40,718 INFO L82 PathProgramCache]: Analyzing trace with hash 706283744, now seen corresponding path program 3 times [2018-11-23 07:20:40,718 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:40,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:40,719 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:20:40,719 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:40,719 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:40,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:20:40,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:20:40,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:20:40,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-23 07:20:40,843 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:20:40,843 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 07:20:40,843 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 07:20:40,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-23 07:20:40,844 INFO L87 Difference]: Start difference. First operand 11338 states and 35212 transitions. Second operand 11 states. [2018-11-23 07:20:41,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:20:41,616 INFO L93 Difference]: Finished difference Result 19630 states and 60855 transitions. [2018-11-23 07:20:41,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 07:20:41,618 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 95 [2018-11-23 07:20:41,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:20:41,636 INFO L225 Difference]: With dead ends: 19630 [2018-11-23 07:20:41,637 INFO L226 Difference]: Without dead ends: 12828 [2018-11-23 07:20:41,637 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=70, Invalid=310, Unknown=0, NotChecked=0, Total=380 [2018-11-23 07:20:41,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12828 states. [2018-11-23 07:20:41,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12828 to 11468. [2018-11-23 07:20:41,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11468 states. [2018-11-23 07:20:41,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11468 states to 11468 states and 35405 transitions. [2018-11-23 07:20:41,801 INFO L78 Accepts]: Start accepts. Automaton has 11468 states and 35405 transitions. Word has length 95 [2018-11-23 07:20:41,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:20:41,801 INFO L480 AbstractCegarLoop]: Abstraction has 11468 states and 35405 transitions. [2018-11-23 07:20:41,801 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 07:20:41,801 INFO L276 IsEmpty]: Start isEmpty. Operand 11468 states and 35405 transitions. [2018-11-23 07:20:41,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-23 07:20:41,813 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:20:41,813 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:20:41,814 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:20:41,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:20:41,814 INFO L82 PathProgramCache]: Analyzing trace with hash -1113263938, now seen corresponding path program 4 times [2018-11-23 07:20:41,814 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:20:41,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:41,815 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:20:41,815 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:20:41,815 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:20:41,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 07:20:41,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 07:20:41,876 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [457] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [337] L-1-->L672: Formula: (= |v_#valid_7| (store |v_#valid_8| 0 0)) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [428] L672-->L674: Formula: (= v_~__unbuffered_cnt~0_8 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_8} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [476] L674-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [325] L676-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [394] L678-->L680: Formula: (= v_~__unbuffered_p2_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 [433] L680-->L682: Formula: (= v_~__unbuffered_p2_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 [491] L682-->L684: Formula: (= v_~a~0_2 0) InVars {} OutVars{~a~0=v_~a~0_2} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 [361] L684-->L685: Formula: (= v_~b~0_3 0) InVars {} OutVars{~b~0=v_~b~0_3} AuxVars[] AssignedVars[~b~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 [474] L685-->L686: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 [398] L686-->L688: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [464] L688-->L690: Formula: (= v_~x~0_4 0) InVars {} OutVars{~x~0=v_~x~0_4} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [498] L690-->L692: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [364] L692-->L693: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [489] L693-->L694: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [426] L694-->L695: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [360] L695-->L696: Formula: (= v_~z$r_buff0_thd0~0_13 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [473] L696-->L697: Formula: (= v_~z$r_buff0_thd1~0_2 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [397] L697-->L698: Formula: (= v_~z$r_buff0_thd2~0_32 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [351] L698-->L699: Formula: (= v_~z$r_buff0_thd3~0_14 0) InVars {} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 [463] L699-->L700: Formula: (= v_~z$r_buff1_thd0~0_9 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [393] L700-->L701: Formula: (= v_~z$r_buff1_thd1~0_2 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [496] L701-->L702: Formula: (= v_~z$r_buff1_thd2~0_18 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_18} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [432] L702-->L703: Formula: (= v_~z$r_buff1_thd3~0_9 0) InVars {} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 [384] L703-->L704: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [488] L704-->L705: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [425] L705-->L706: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [359] L706-->L707: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [470] L707-->L708: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [396] L708-->L709: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [348] L709-->L710: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [462] L710-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [487] L-1-2-->L806: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_3|, ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_1|, ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_1|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_4|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_3|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_3|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_2|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_3|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t884~0.base, ULTIMATE.start_main_#t~nondet36, ULTIMATE.start_main_#t~nondet35, ULTIMATE.start_main_~#t886~0.base, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t885~0.base, ULTIMATE.start_main_~#t885~0.offset, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet37, ULTIMATE.start_main_~#t884~0.offset, ULTIMATE.start_main_~#t886~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [480] L806-->L806-1: Formula: (and (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t884~0.base_4|)) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t884~0.base_4| 4)) (= |v_ULTIMATE.start_main_~#t884~0.offset_4| 0) (= (store |v_#valid_10| |v_ULTIMATE.start_main_~#t884~0.base_4| 1) |v_#valid_9|) (not (= |v_ULTIMATE.start_main_~#t884~0.base_4| 0))) InVars {#length=|v_#length_2|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_4|, #length=|v_#length_1|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t884~0.base, #valid, ULTIMATE.start_main_~#t884~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [483] L806-1-->L807: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t884~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t884~0.base_5|) |v_ULTIMATE.start_main_~#t884~0.offset_5| 0)) |v_#memory_int_3|) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [603] L807-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [416] L807-1-->L808: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet35] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [342] L808-->L808-1: Formula: (and (= |v_ULTIMATE.start_main_~#t885~0.offset_4| 0) (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t885~0.base_4|) 0) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t885~0.base_4| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t885~0.base_4| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t885~0.base_4| 4))) InVars {#length=|v_#length_4|, #valid=|v_#valid_12|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_4|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_4|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t885~0.base, ULTIMATE.start_main_~#t885~0.offset] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [343] L808-1-->L809: Formula: (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t885~0.base_5| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t885~0.base_5|) |v_ULTIMATE.start_main_~#t885~0.offset_5| 1)) |v_#memory_int_5|) InVars {#memory_int=|v_#memory_int_6|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_5|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_5|} OutVars{#memory_int=|v_#memory_int_5|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_5|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [604] L809-->P1ENTRY: Formula: (and (= |v_Thread2_P1_#in~arg.base_3| 0) (= v_Thread2_P1_thidvar0_2 1) (= 0 |v_Thread2_P1_#in~arg.offset_3|)) InVars {} OutVars{Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_3|, Thread2_P1_thidvar0=v_Thread2_P1_thidvar0_2, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread2_P1_#in~arg.base, Thread2_P1_thidvar0, Thread2_P1_#in~arg.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L809-1-->L810: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet36] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [408] L810-->L810-1: Formula: (and (= 0 (select |v_#valid_14| |v_ULTIMATE.start_main_~#t886~0.base_5|)) (= |v_ULTIMATE.start_main_~#t886~0.offset_5| 0) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#t886~0.base_5| 4) |v_#length_5|) (not (= |v_ULTIMATE.start_main_~#t886~0.base_5| 0)) (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t886~0.base_5| 1))) InVars {#length=|v_#length_6|, #valid=|v_#valid_14|} OutVars{ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_5|, #length=|v_#length_5|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_5|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t886~0.base, #length, ULTIMATE.start_main_~#t886~0.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [385] L810-1-->L811: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t886~0.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t886~0.base_1|) |v_ULTIMATE.start_main_~#t886~0.offset_1| 2))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_1|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_1|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_1|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_1|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [602] L811-->P2ENTRY: Formula: (and (= |v_Thread0_P2_#in~arg.offset_3| 0) (= 0 |v_Thread0_P2_#in~arg.base_3|) (= 2 v_Thread0_P2_thidvar0_2)) InVars {} OutVars{Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_3|, Thread0_P2_thidvar0=v_Thread0_P2_thidvar0_2, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P2_#in~arg.base, Thread0_P2_thidvar0, Thread0_P2_#in~arg.offset] VAL [Thread0_P2_thidvar0=2, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [575] P2ENTRY-->L4: Formula: (and (= v_Thread0_P2_~arg.offset_1 |v_Thread0_P2_#in~arg.offset_1|) (= |v_Thread0_P2___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= (mod v_~z$w_buff1_used~0_21 256) 0)) (not (= (mod v_~z$w_buff0_used~0_36 256) 0)))) 1 0)) (= v_Thread0_P2___VERIFIER_assert_~expression_1 |v_Thread0_P2___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_36 1) (= v_Thread0_P2_~arg.base_1 |v_Thread0_P2_#in~arg.base_1|) (= v_~z$w_buff0~0_7 1) (= v_~z$w_buff1_used~0_21 v_~z$w_buff0_used~0_37) (= v_~z$w_buff1~0_7 v_~z$w_buff0~0_8)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_37, ~z$w_buff0~0=v_~z$w_buff0~0_8, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|} OutVars{Thread0_P2_~arg.offset=v_Thread0_P2_~arg.offset_1, Thread0_P2_~arg.base=v_Thread0_P2_~arg.base_1, Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_36, ~z$w_buff0~0=v_~z$w_buff0~0_7, Thread0_P2___VERIFIER_assert_#in~expression=|v_Thread0_P2___VERIFIER_assert_#in~expression_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_21, ~z$w_buff1~0=v_~z$w_buff1~0_7, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P2_~arg.offset, Thread0_P2_~arg.base, Thread0_P2___VERIFIER_assert_~expression, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P2___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [577] L4-->L4-3: Formula: (not (= 0 v_Thread0_P2___VERIFIER_assert_~expression_3)) InVars {Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} OutVars{Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [580] L4-3-->L784: Formula: (and (= v_~z$r_buff1_thd2~0_17 v_~z$r_buff0_thd2~0_31) (= v_~a~0_1 1) (= v_~__unbuffered_p2_EAX~0_1 v_~a~0_1) (= v_~__unbuffered_p2_EBX~0_1 v_~b~0_2) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_1) (= v_~z$r_buff0_thd3~0_7 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd3~0_5 v_~z$r_buff0_thd3~0_8)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~b~0=v_~b~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_1, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~a~0=v_~a~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~b~0=v_~b~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p2_EBX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [581] L784-->L784-5: Formula: (and (= |v_Thread0_P2_#t~ite29_1| v_~z$w_buff0~0_9) (not (= (mod v_~z$w_buff0_used~0_38 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd3~0_9 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} AuxVars[] AssignedVars[Thread0_P2_#t~ite29] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [504] P0ENTRY-->L724: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~b~0_1 1) (= v_~x~0_1 1)) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~b~0=v_~b~0_1, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[Thread1_P0_~arg.offset, ~b~0, Thread1_P0_~arg.base, ~__unbuffered_cnt~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [508] P1ENTRY-->L742: Formula: (and (= v_Thread2_P1_~arg.offset_1 |v_Thread2_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_1) (= v_~weak$$choice2~0_2 (ite (= (+ |v_Thread2_P1_#t~nondet5.base_1| |v_Thread2_P1_#t~nondet5.offset_1|) 0) 0 1)) (= v_Thread2_P1_~arg.base_1 |v_Thread2_P1_#in~arg.base_1|) (= v_~x~0_2 2) (= v_~weak$$choice0~0_1 (ite (= (+ |v_Thread2_P1_#t~nondet4.base_1| |v_Thread2_P1_#t~nondet4.offset_1|) 0) 0 1)) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~y~0_1 1)) InVars {Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_1|, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_1|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_1|, ~z~0=v_~z~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_1|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_~arg.offset=v_Thread2_P1_~arg.offset_1, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_2|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread2_P1_~arg.base=v_Thread2_P1_~arg.base_1, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_2|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_2, ~y~0=v_~y~0_1, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread2_P1_~arg.offset, Thread2_P1_#t~nondet5.base, ~z$flush_delayed~0, Thread2_P1_#t~nondet4.offset, ~weak$$choice0~0, ~__unbuffered_p1_EAX~0, Thread2_P1_~arg.base, Thread2_P1_#t~nondet5.offset, Thread2_P1_#t~nondet4.base, ~weak$$choice2~0, ~y~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [509] L742-->L742-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_3 256) 0))) (or (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_3 256))) (= (mod v_~z$w_buff0_used~0_3 256) 0) (and (= 0 (mod v_~z$w_buff1_used~0_3 256)) .cse0))) (= |v_Thread2_P1_#t~ite7_1| v_~z~0_2)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3, Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3} AuxVars[] AssignedVars[Thread2_P1_#t~ite7] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [583] L784-5-->L785: Formula: (= v_~z~0_8 |v_Thread0_P2_#t~ite29_2|) InVars {Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_2|} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_3|, Thread0_P2_#t~ite28=|v_Thread0_P2_#t~ite28_1|, ~z~0=v_~z~0_8} AuxVars[] AssignedVars[Thread0_P2_#t~ite29, Thread0_P2_#t~ite28, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [586] L785-->L785-2: Formula: (and (not (= 0 (mod v_~z$w_buff0_used~0_40 256))) (= |v_Thread0_P2_#t~ite30_1| 0) (not (= 0 (mod v_~z$r_buff0_thd3~0_11 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite30|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [589] L785-2-->L786: Formula: (= v_~z$w_buff0_used~0_42 |v_Thread0_P2_#t~ite30_3|) InVars {Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_3|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_42, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [591] L786-->L786-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_1 256)) (= 0 (mod v_~z$w_buff0_used~0_31 256))) (or (= (mod v_~z$w_buff1_used~0_17 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_1 256))) (= |v_Thread0_P2_#t~ite31_2| v_~z$w_buff1_used~0_17)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} AuxVars[] AssignedVars[Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite31|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [592] L786-2-->L787: Formula: (= v_~z$w_buff1_used~0_18 |v_Thread0_P2_#t~ite31_3|) InVars {Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_18, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [594] L787-->L787-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_3 256)) (= (mod v_~z$w_buff0_used~0_33 256) 0)) (= |v_Thread0_P2_#t~ite32_2| v_~z$r_buff0_thd3~0_3)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_33, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_33} AuxVars[] AssignedVars[Thread0_P2_#t~ite32] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite32|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [595] L787-2-->L788: Formula: (= v_~z$r_buff0_thd3~0_4 |v_Thread0_P2_#t~ite32_3|) InVars {Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_3|} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_4|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_4} AuxVars[] AssignedVars[Thread0_P2_#t~ite32, ~z$r_buff0_thd3~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [597] L788-->L788-2: Formula: (and (= |v_Thread0_P2_#t~ite33_2| v_~z$r_buff1_thd3~0_3) (or (= 0 (mod v_~z$r_buff0_thd3~0_6 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) (or (= (mod v_~z$r_buff1_thd3~0_3 256) 0) (= (mod v_~z$w_buff1_used~0_20 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} AuxVars[] AssignedVars[Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite33|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [598] L788-2-->L793: Formula: (and (= v_~z$r_buff1_thd3~0_4 |v_Thread0_P2_#t~ite33_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_4|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_4} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 [511] L742-5-->L743: Formula: (= v_~z~0_4 |v_Thread2_P1_#t~ite7_2|) InVars {Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_2|} OutVars{Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_3|, ~z~0=v_~z~0_4, Thread2_P1_#t~ite6=|v_Thread2_P1_#t~ite6_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite7, ~z~0, Thread2_P1_#t~ite6] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [514] L743-->L743-8: Formula: (and (= |v_Thread2_P1_#t~ite10_1| v_~z$w_buff0~0_2) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite10] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite10|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [517] L743-8-->L744: Formula: (= v_~z$w_buff0~0_6 |v_Thread2_P1_#t~ite10_2|) InVars {Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_2|} OutVars{Thread2_P1_#t~ite8=|v_Thread2_P1_#t~ite8_1|, Thread2_P1_#t~ite9=|v_Thread2_P1_#t~ite9_1|, ~z$w_buff0~0=v_~z$w_buff0~0_6, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_3|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread2_P1_#t~ite10, Thread2_P1_#t~ite8, Thread2_P1_#t~ite9] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [520] L744-->L744-8: Formula: (and (= |v_Thread2_P1_#t~ite13_1| v_~z$w_buff1~0_2) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$w_buff1~0=v_~z$w_buff1~0_2} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_1|, ~z$w_buff1~0=v_~z$w_buff1~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread2_P1_#t~ite13] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [525] L744-8-->L745: Formula: (= v_~z$w_buff1~0_6 |v_Thread2_P1_#t~ite13_2|) InVars {Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_2|} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_3|, Thread2_P1_#t~ite12=|v_Thread2_P1_#t~ite12_1|, ~z$w_buff1~0=v_~z$w_buff1~0_6, Thread2_P1_#t~ite11=|v_Thread2_P1_#t~ite11_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite11, Thread2_P1_#t~ite13, Thread2_P1_#t~ite12, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [529] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_7 256))) (= |v_Thread2_P1_#t~ite16_1| v_~z$w_buff0_used~0_17)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite16|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [534] L745-8-->L746: Formula: (= v_~z$w_buff0_used~0_22 |v_Thread2_P1_#t~ite16_2|) InVars {Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_2|} OutVars{Thread2_P1_#t~ite15=|v_Thread2_P1_#t~ite15_1|, Thread2_P1_#t~ite14=|v_Thread2_P1_#t~ite14_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_22, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread2_P1_#t~ite15, Thread2_P1_#t~ite14, Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [538] L746-->L746-8: Formula: (and (= |v_Thread2_P1_#t~ite19_1| v_~z$w_buff1_used~0_11) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite19] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [543] L746-8-->L747: Formula: (= v_~z$w_buff1_used~0_14 |v_Thread2_P1_#t~ite19_2|) InVars {Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_2|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_14, Thread2_P1_#t~ite17=|v_Thread2_P1_#t~ite17_1|, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_3|, Thread2_P1_#t~ite18=|v_Thread2_P1_#t~ite18_1|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread2_P1_#t~ite17, Thread2_P1_#t~ite19, Thread2_P1_#t~ite18] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [547] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_Thread2_P1_#t~ite22_1| v_~z$r_buff0_thd2~0_25)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[Thread2_P1_#t~ite22] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite22|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [552] L747-8-->L748: Formula: (= v_~z$r_buff0_thd2~0_30 |v_Thread2_P1_#t~ite22_2|) InVars {Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_2|} OutVars{Thread2_P1_#t~ite21=|v_Thread2_P1_#t~ite21_1|, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_3|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_30, Thread2_P1_#t~ite20=|v_Thread2_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite21, Thread2_P1_#t~ite22, Thread2_P1_#t~ite20, ~z$r_buff0_thd2~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [556] L748-->L748-8: Formula: (and (not (= (mod v_~weak$$choice2~0_13 256) 0)) (= |v_Thread2_P1_#t~ite25_1| v_~z$r_buff1_thd2~0_16)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} OutVars{Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} AuxVars[] AssignedVars[Thread2_P1_#t~ite25] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [561] L748-8-->L750: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_3) (= v_~z$r_buff1_thd2~0_5 |v_Thread2_P1_#t~ite25_2|)) InVars {Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_2|, ~z~0=v_~z~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_5, Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_3|, Thread2_P1_#t~ite23=|v_Thread2_P1_#t~ite23_1|, Thread2_P1_#t~ite24=|v_Thread2_P1_#t~ite24_1|, ~z~0=v_~z~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, ~z$r_buff1_thd2~0, Thread2_P1_#t~ite25, Thread2_P1_#t~ite23, Thread2_P1_#t~ite24] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [565] L750-->L750-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread2_P1_#t~ite26_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_1|, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} AuxVars[] AssignedVars[Thread2_P1_#t~ite26] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite26|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [570] L750-2-->L758: Formula: (and (= v_~z~0_6 |v_Thread2_P1_#t~ite26_3|) (= v_~z$flush_delayed~0_4 0) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread2_P1_#t~ite26, ~__unbuffered_cnt~0, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [336] L811-1-->L815: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet37, ~main$tmp_guard0~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [444] L815-->L817: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L817-->L817-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_45 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [485] L817-2-->L817-4: Formula: (and (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd0~0_3 256) 0)) (= |v_ULTIMATE.start_main_#t~ite38_2| v_~z~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_2|, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [475] L817-4-->L817-5: Formula: (= |v_ULTIMATE.start_main_#t~ite39_2| |v_ULTIMATE.start_main_#t~ite38_3|) InVars {ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_2|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [477] L817-5-->L818: Formula: (= v_~z~0_10 |v_ULTIMATE.start_main_#t~ite39_4|) InVars {ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} OutVars{ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ~z~0=v_~z~0_10, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [412] L818-->L818-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= (mod v_~z$w_buff0_used~0_47 256) 0)) (= |v_ULTIMATE.start_main_#t~ite40_2| v_~z$w_buff0_used~0_47)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_47, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L818-2-->L819: Formula: (= v_~z$w_buff0_used~0_48 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ~z$w_buff0_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [341] L819-->L819-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite41_2| v_~z$w_buff1_used~0_28) (or (= 0 (mod v_~z$w_buff0_used~0_50 256)) (= 0 (mod v_~z$r_buff0_thd0~0_7 256))) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= (mod v_~z$w_buff1_used~0_28 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_2|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [345] L819-2-->L820: Formula: (= v_~z$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite41_4|) InVars {ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$w_buff1_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [453] L820-->L820-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_2| v_~z$r_buff0_thd0~0_9) (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_52 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [459] L820-2-->L821: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L821-->L821-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_12 256) 0) (= 0 (mod v_~z$w_buff0_used~0_54 256))) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_31 256) 0)) (= |v_ULTIMATE.start_main_#t~ite43_2| v_~z$r_buff1_thd0~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [388] L821-2-->L826: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite43_4|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= 2 v_~x~0_3) (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ~x~0=v_~x~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [443] L826-->L826-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [421] L826-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [379] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [375] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [371] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0, main_~#t885~0, main_~#t886~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0, main_~#t885~0, main_~#t886~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t884; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t884, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t885; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t885, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t886; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t886, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-23 07:20:44,171 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 07:20:44,172 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 07:20:44 BasicIcfg [2018-11-23 07:20:44,173 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 07:20:44,173 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 07:20:44,173 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 07:20:44,173 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 07:20:44,202 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:19:34" (3/4) ... [2018-11-23 07:20:44,204 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [457] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [337] L-1-->L672: Formula: (= |v_#valid_7| (store |v_#valid_8| 0 0)) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [428] L672-->L674: Formula: (= v_~__unbuffered_cnt~0_8 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_8} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [476] L674-->L676: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [325] L676-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [394] L678-->L680: Formula: (= v_~__unbuffered_p2_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 [433] L680-->L682: Formula: (= v_~__unbuffered_p2_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p2_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 [491] L682-->L684: Formula: (= v_~a~0_2 0) InVars {} OutVars{~a~0=v_~a~0_2} AuxVars[] AssignedVars[~a~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 [361] L684-->L685: Formula: (= v_~b~0_3 0) InVars {} OutVars{~b~0=v_~b~0_3} AuxVars[] AssignedVars[~b~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 [474] L685-->L686: Formula: (= v_~main$tmp_guard0~0_3 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 [398] L686-->L688: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [464] L688-->L690: Formula: (= v_~x~0_4 0) InVars {} OutVars{~x~0=v_~x~0_4} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [498] L690-->L692: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [364] L692-->L693: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [489] L693-->L694: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [426] L694-->L695: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [360] L695-->L696: Formula: (= v_~z$r_buff0_thd0~0_13 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [473] L696-->L697: Formula: (= v_~z$r_buff0_thd1~0_2 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [397] L697-->L698: Formula: (= v_~z$r_buff0_thd2~0_32 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [351] L698-->L699: Formula: (= v_~z$r_buff0_thd3~0_14 0) InVars {} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 [463] L699-->L700: Formula: (= v_~z$r_buff1_thd0~0_9 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [393] L700-->L701: Formula: (= v_~z$r_buff1_thd1~0_2 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [496] L701-->L702: Formula: (= v_~z$r_buff1_thd2~0_18 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_18} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [432] L702-->L703: Formula: (= v_~z$r_buff1_thd3~0_9 0) InVars {} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd3~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 [384] L703-->L704: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [488] L704-->L705: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [425] L705-->L706: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [359] L706-->L707: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [470] L707-->L708: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [396] L708-->L709: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [348] L709-->L710: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [462] L710-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [490] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [487] L-1-2-->L806: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_3|, ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_1|, ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_1|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_4|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_3|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_3|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_2|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_3|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t884~0.base, ULTIMATE.start_main_#t~nondet36, ULTIMATE.start_main_#t~nondet35, ULTIMATE.start_main_~#t886~0.base, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t885~0.base, ULTIMATE.start_main_~#t885~0.offset, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet37, ULTIMATE.start_main_~#t884~0.offset, ULTIMATE.start_main_~#t886~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [480] L806-->L806-1: Formula: (and (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t884~0.base_4|)) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t884~0.base_4| 4)) (= |v_ULTIMATE.start_main_~#t884~0.offset_4| 0) (= (store |v_#valid_10| |v_ULTIMATE.start_main_~#t884~0.base_4| 1) |v_#valid_9|) (not (= |v_ULTIMATE.start_main_~#t884~0.base_4| 0))) InVars {#length=|v_#length_2|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_4|, #length=|v_#length_1|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t884~0.base, #valid, ULTIMATE.start_main_~#t884~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [483] L806-1-->L807: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t884~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t884~0.base_5|) |v_ULTIMATE.start_main_~#t884~0.offset_5| 0)) |v_#memory_int_3|) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t884~0.offset=|v_ULTIMATE.start_main_~#t884~0.offset_5|, ULTIMATE.start_main_~#t884~0.base=|v_ULTIMATE.start_main_~#t884~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [603] L807-->P0ENTRY: Formula: (and (= 0 |v_Thread1_P0_#in~arg.base_3|) (= 0 v_Thread1_P0_thidvar0_2) (= 0 |v_Thread1_P0_#in~arg.offset_3|)) InVars {} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_3|, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_3|, Thread1_P0_thidvar0=v_Thread1_P0_thidvar0_2} AuxVars[] AssignedVars[Thread1_P0_#in~arg.base, Thread1_P0_#in~arg.offset, Thread1_P0_thidvar0] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [416] L807-1-->L808: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet35=|v_ULTIMATE.start_main_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet35] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [342] L808-->L808-1: Formula: (and (= |v_ULTIMATE.start_main_~#t885~0.offset_4| 0) (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t885~0.base_4|) 0) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t885~0.base_4| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t885~0.base_4| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t885~0.base_4| 4))) InVars {#length=|v_#length_4|, #valid=|v_#valid_12|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_4|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_4|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t885~0.base, ULTIMATE.start_main_~#t885~0.offset] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [343] L808-1-->L809: Formula: (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t885~0.base_5| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t885~0.base_5|) |v_ULTIMATE.start_main_~#t885~0.offset_5| 1)) |v_#memory_int_5|) InVars {#memory_int=|v_#memory_int_6|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_5|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_5|} OutVars{#memory_int=|v_#memory_int_5|, ULTIMATE.start_main_~#t885~0.base=|v_ULTIMATE.start_main_~#t885~0.base_5|, ULTIMATE.start_main_~#t885~0.offset=|v_ULTIMATE.start_main_~#t885~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [604] L809-->P1ENTRY: Formula: (and (= |v_Thread2_P1_#in~arg.base_3| 0) (= v_Thread2_P1_thidvar0_2 1) (= 0 |v_Thread2_P1_#in~arg.offset_3|)) InVars {} OutVars{Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_3|, Thread2_P1_thidvar0=v_Thread2_P1_thidvar0_2, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread2_P1_#in~arg.base, Thread2_P1_thidvar0, Thread2_P1_#in~arg.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L809-1-->L810: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet36=|v_ULTIMATE.start_main_#t~nondet36_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet36] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [408] L810-->L810-1: Formula: (and (= 0 (select |v_#valid_14| |v_ULTIMATE.start_main_~#t886~0.base_5|)) (= |v_ULTIMATE.start_main_~#t886~0.offset_5| 0) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#t886~0.base_5| 4) |v_#length_5|) (not (= |v_ULTIMATE.start_main_~#t886~0.base_5| 0)) (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t886~0.base_5| 1))) InVars {#length=|v_#length_6|, #valid=|v_#valid_14|} OutVars{ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_5|, #length=|v_#length_5|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_5|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#t886~0.base, #length, ULTIMATE.start_main_~#t886~0.offset] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [385] L810-1-->L811: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t886~0.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t886~0.base_1|) |v_ULTIMATE.start_main_~#t886~0.offset_1| 2))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_1|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_1|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t886~0.base=|v_ULTIMATE.start_main_~#t886~0.base_1|, ULTIMATE.start_main_~#t886~0.offset=|v_ULTIMATE.start_main_~#t886~0.offset_1|} AuxVars[] AssignedVars[#memory_int] VAL [Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [602] L811-->P2ENTRY: Formula: (and (= |v_Thread0_P2_#in~arg.offset_3| 0) (= 0 |v_Thread0_P2_#in~arg.base_3|) (= 2 v_Thread0_P2_thidvar0_2)) InVars {} OutVars{Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_3|, Thread0_P2_thidvar0=v_Thread0_P2_thidvar0_2, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P2_#in~arg.base, Thread0_P2_thidvar0, Thread0_P2_#in~arg.offset] VAL [Thread0_P2_thidvar0=2, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [575] P2ENTRY-->L4: Formula: (and (= v_Thread0_P2_~arg.offset_1 |v_Thread0_P2_#in~arg.offset_1|) (= |v_Thread0_P2___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= (mod v_~z$w_buff1_used~0_21 256) 0)) (not (= (mod v_~z$w_buff0_used~0_36 256) 0)))) 1 0)) (= v_Thread0_P2___VERIFIER_assert_~expression_1 |v_Thread0_P2___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_36 1) (= v_Thread0_P2_~arg.base_1 |v_Thread0_P2_#in~arg.base_1|) (= v_~z$w_buff0~0_7 1) (= v_~z$w_buff1_used~0_21 v_~z$w_buff0_used~0_37) (= v_~z$w_buff1~0_7 v_~z$w_buff0~0_8)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_37, ~z$w_buff0~0=v_~z$w_buff0~0_8, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|} OutVars{Thread0_P2_~arg.offset=v_Thread0_P2_~arg.offset_1, Thread0_P2_~arg.base=v_Thread0_P2_~arg.base_1, Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_36, ~z$w_buff0~0=v_~z$w_buff0~0_7, Thread0_P2___VERIFIER_assert_#in~expression=|v_Thread0_P2___VERIFIER_assert_#in~expression_1|, Thread0_P2_#in~arg.base=|v_Thread0_P2_#in~arg.base_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_21, ~z$w_buff1~0=v_~z$w_buff1~0_7, Thread0_P2_#in~arg.offset=|v_Thread0_P2_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P2_~arg.offset, Thread0_P2_~arg.base, Thread0_P2___VERIFIER_assert_~expression, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P2___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [577] L4-->L4-3: Formula: (not (= 0 v_Thread0_P2___VERIFIER_assert_~expression_3)) InVars {Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} OutVars{Thread0_P2___VERIFIER_assert_~expression=v_Thread0_P2___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [580] L4-3-->L784: Formula: (and (= v_~z$r_buff1_thd2~0_17 v_~z$r_buff0_thd2~0_31) (= v_~a~0_1 1) (= v_~__unbuffered_p2_EAX~0_1 v_~a~0_1) (= v_~__unbuffered_p2_EBX~0_1 v_~b~0_2) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_1) (= v_~z$r_buff0_thd3~0_7 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd3~0_5 v_~z$r_buff0_thd3~0_8)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_8, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~b~0=v_~b~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} OutVars{~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_1, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~a~0=v_~a~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~b~0=v_~b~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_7, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_31} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p2_EBX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [581] L784-->L784-5: Formula: (and (= |v_Thread0_P2_#t~ite29_1| v_~z$w_buff0~0_9) (not (= (mod v_~z$w_buff0_used~0_38 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd3~0_9 256)))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_1|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_9, ~z$w_buff0~0=v_~z$w_buff0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_38} AuxVars[] AssignedVars[Thread0_P2_#t~ite29] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [504] P0ENTRY-->L724: Formula: (and (= v_Thread1_P0_~arg.base_1 |v_Thread1_P0_#in~arg.base_1|) (= v_Thread1_P0_~arg.offset_1 |v_Thread1_P0_#in~arg.offset_1|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1)) (= v_~b~0_1 1) (= v_~x~0_1 1)) InVars {Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{Thread1_P0_#in~arg.base=|v_Thread1_P0_#in~arg.base_1|, Thread1_P0_~arg.offset=v_Thread1_P0_~arg.offset_1, ~b~0=v_~b~0_1, Thread1_P0_~arg.base=v_Thread1_P0_~arg.base_1, Thread1_P0_#in~arg.offset=|v_Thread1_P0_#in~arg.offset_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x~0=v_~x~0_1} AuxVars[] AssignedVars[Thread1_P0_~arg.offset, ~b~0, Thread1_P0_~arg.base, ~__unbuffered_cnt~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [508] P1ENTRY-->L742: Formula: (and (= v_Thread2_P1_~arg.offset_1 |v_Thread2_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_1) (= v_~weak$$choice2~0_2 (ite (= (+ |v_Thread2_P1_#t~nondet5.base_1| |v_Thread2_P1_#t~nondet5.offset_1|) 0) 0 1)) (= v_Thread2_P1_~arg.base_1 |v_Thread2_P1_#in~arg.base_1|) (= v_~x~0_2 2) (= v_~weak$$choice0~0_1 (ite (= (+ |v_Thread2_P1_#t~nondet4.base_1| |v_Thread2_P1_#t~nondet4.offset_1|) 0) 0 1)) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_2) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~y~0_1 1)) InVars {Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_1|, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_1|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_1|, ~z~0=v_~z~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_1|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread2_P1_#in~arg.base=|v_Thread2_P1_#in~arg.base_1|, Thread2_P1_~arg.offset=v_Thread2_P1_~arg.offset_1, Thread2_P1_#t~nondet5.base=|v_Thread2_P1_#t~nondet5.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread2_P1_#t~nondet4.offset=|v_Thread2_P1_#t~nondet4.offset_2|, Thread2_P1_#in~arg.offset=|v_Thread2_P1_#in~arg.offset_1|, ~weak$$choice0~0=v_~weak$$choice0~0_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread2_P1_~arg.base=v_Thread2_P1_~arg.base_1, Thread2_P1_#t~nondet5.offset=|v_Thread2_P1_#t~nondet5.offset_2|, Thread2_P1_#t~nondet4.base=|v_Thread2_P1_#t~nondet4.base_2|, ~z~0=v_~z~0_1, ~weak$$choice2~0=v_~weak$$choice2~0_2, ~y~0=v_~y~0_1, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread2_P1_~arg.offset, Thread2_P1_#t~nondet5.base, ~z$flush_delayed~0, Thread2_P1_#t~nondet4.offset, ~weak$$choice0~0, ~__unbuffered_p1_EAX~0, Thread2_P1_~arg.base, Thread2_P1_#t~nondet5.offset, Thread2_P1_#t~nondet4.base, ~weak$$choice2~0, ~y~0, ~x~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [509] L742-->L742-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_3 256) 0))) (or (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_3 256))) (= (mod v_~z$w_buff0_used~0_3 256) 0) (and (= 0 (mod v_~z$w_buff1_used~0_3 256)) .cse0))) (= |v_Thread2_P1_#t~ite7_1| v_~z~0_2)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_3, Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_3, ~z~0=v_~z~0_2, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_3} AuxVars[] AssignedVars[Thread2_P1_#t~ite7] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite29|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [583] L784-5-->L785: Formula: (= v_~z~0_8 |v_Thread0_P2_#t~ite29_2|) InVars {Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_2|} OutVars{Thread0_P2_#t~ite29=|v_Thread0_P2_#t~ite29_3|, Thread0_P2_#t~ite28=|v_Thread0_P2_#t~ite28_1|, ~z~0=v_~z~0_8} AuxVars[] AssignedVars[Thread0_P2_#t~ite29, Thread0_P2_#t~ite28, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [586] L785-->L785-2: Formula: (and (not (= 0 (mod v_~z$w_buff0_used~0_40 256))) (= |v_Thread0_P2_#t~ite30_1| 0) (not (= 0 (mod v_~z$r_buff0_thd3~0_11 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11} OutVars{~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_11, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_1|} AuxVars[] AssignedVars[Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite30|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [589] L785-2-->L786: Formula: (= v_~z$w_buff0_used~0_42 |v_Thread0_P2_#t~ite30_3|) InVars {Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_3|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_42, Thread0_P2_#t~ite30=|v_Thread0_P2_#t~ite30_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P2_#t~ite30] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [591] L786-->L786-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_1 256)) (= 0 (mod v_~z$w_buff0_used~0_31 256))) (or (= (mod v_~z$w_buff1_used~0_17 256) 0) (= 0 (mod v_~z$r_buff1_thd3~0_1 256))) (= |v_Thread0_P2_#t~ite31_2| v_~z$w_buff1_used~0_17)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_1, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_31, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_1} AuxVars[] AssignedVars[Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite31|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [592] L786-2-->L787: Formula: (= v_~z$w_buff1_used~0_18 |v_Thread0_P2_#t~ite31_3|) InVars {Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_18, Thread0_P2_#t~ite31=|v_Thread0_P2_#t~ite31_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P2_#t~ite31] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [594] L787-->L787-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd3~0_3 256)) (= (mod v_~z$w_buff0_used~0_33 256) 0)) (= |v_Thread0_P2_#t~ite32_2| v_~z$r_buff0_thd3~0_3)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_33, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_2|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_33} AuxVars[] AssignedVars[Thread0_P2_#t~ite32] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite32|=1, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [595] L787-2-->L788: Formula: (= v_~z$r_buff0_thd3~0_4 |v_Thread0_P2_#t~ite32_3|) InVars {Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_3|} OutVars{Thread0_P2_#t~ite32=|v_Thread0_P2_#t~ite32_4|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_4} AuxVars[] AssignedVars[Thread0_P2_#t~ite32, ~z$r_buff0_thd3~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [597] L788-->L788-2: Formula: (and (= |v_Thread0_P2_#t~ite33_2| v_~z$r_buff1_thd3~0_3) (or (= 0 (mod v_~z$r_buff0_thd3~0_6 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) (or (= (mod v_~z$r_buff1_thd3~0_3 256) 0) (= (mod v_~z$w_buff1_used~0_20 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_20, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_3} AuxVars[] AssignedVars[Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2_#t~ite33|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [598] L788-2-->L793: Formula: (and (= v_~z$r_buff1_thd3~0_4 |v_Thread0_P2_#t~ite33_3|) (= v_~__unbuffered_cnt~0_5 (+ v_~__unbuffered_cnt~0_6 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, Thread0_P2_#t~ite33=|v_Thread0_P2_#t~ite33_4|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_4} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, Thread0_P2_#t~ite33] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite7|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 [511] L742-5-->L743: Formula: (= v_~z~0_4 |v_Thread2_P1_#t~ite7_2|) InVars {Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_2|} OutVars{Thread2_P1_#t~ite7=|v_Thread2_P1_#t~ite7_3|, ~z~0=v_~z~0_4, Thread2_P1_#t~ite6=|v_Thread2_P1_#t~ite6_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite7, ~z~0, Thread2_P1_#t~ite6] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [514] L743-->L743-8: Formula: (and (= |v_Thread2_P1_#t~ite10_1| v_~z$w_buff0~0_2) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite10] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite10|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [517] L743-8-->L744: Formula: (= v_~z$w_buff0~0_6 |v_Thread2_P1_#t~ite10_2|) InVars {Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_2|} OutVars{Thread2_P1_#t~ite8=|v_Thread2_P1_#t~ite8_1|, Thread2_P1_#t~ite9=|v_Thread2_P1_#t~ite9_1|, ~z$w_buff0~0=v_~z$w_buff0~0_6, Thread2_P1_#t~ite10=|v_Thread2_P1_#t~ite10_3|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread2_P1_#t~ite10, Thread2_P1_#t~ite8, Thread2_P1_#t~ite9] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [520] L744-->L744-8: Formula: (and (= |v_Thread2_P1_#t~ite13_1| v_~z$w_buff1~0_2) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$w_buff1~0=v_~z$w_buff1~0_2} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_1|, ~z$w_buff1~0=v_~z$w_buff1~0_2, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[Thread2_P1_#t~ite13] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [525] L744-8-->L745: Formula: (= v_~z$w_buff1~0_6 |v_Thread2_P1_#t~ite13_2|) InVars {Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_2|} OutVars{Thread2_P1_#t~ite13=|v_Thread2_P1_#t~ite13_3|, Thread2_P1_#t~ite12=|v_Thread2_P1_#t~ite12_1|, ~z$w_buff1~0=v_~z$w_buff1~0_6, Thread2_P1_#t~ite11=|v_Thread2_P1_#t~ite11_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite11, Thread2_P1_#t~ite13, Thread2_P1_#t~ite12, ~z$w_buff1~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [529] L745-->L745-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_7 256))) (= |v_Thread2_P1_#t~ite16_1| v_~z$w_buff0_used~0_17)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_17, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite16|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [534] L745-8-->L746: Formula: (= v_~z$w_buff0_used~0_22 |v_Thread2_P1_#t~ite16_2|) InVars {Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_2|} OutVars{Thread2_P1_#t~ite15=|v_Thread2_P1_#t~ite15_1|, Thread2_P1_#t~ite14=|v_Thread2_P1_#t~ite14_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_22, Thread2_P1_#t~ite16=|v_Thread2_P1_#t~ite16_3|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread2_P1_#t~ite15, Thread2_P1_#t~ite14, Thread2_P1_#t~ite16] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [538] L746-->L746-8: Formula: (and (= |v_Thread2_P1_#t~ite19_1| v_~z$w_buff1_used~0_11) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_11, ~weak$$choice2~0=v_~weak$$choice2~0_9, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite19] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [543] L746-8-->L747: Formula: (= v_~z$w_buff1_used~0_14 |v_Thread2_P1_#t~ite19_2|) InVars {Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_2|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_14, Thread2_P1_#t~ite17=|v_Thread2_P1_#t~ite17_1|, Thread2_P1_#t~ite19=|v_Thread2_P1_#t~ite19_3|, Thread2_P1_#t~ite18=|v_Thread2_P1_#t~ite18_1|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread2_P1_#t~ite17, Thread2_P1_#t~ite19, Thread2_P1_#t~ite18] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [547] L747-->L747-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_Thread2_P1_#t~ite22_1| v_~z$r_buff0_thd2~0_25)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[Thread2_P1_#t~ite22] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite22|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [552] L747-8-->L748: Formula: (= v_~z$r_buff0_thd2~0_30 |v_Thread2_P1_#t~ite22_2|) InVars {Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_2|} OutVars{Thread2_P1_#t~ite21=|v_Thread2_P1_#t~ite21_1|, Thread2_P1_#t~ite22=|v_Thread2_P1_#t~ite22_3|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_30, Thread2_P1_#t~ite20=|v_Thread2_P1_#t~ite20_1|} AuxVars[] AssignedVars[Thread2_P1_#t~ite21, Thread2_P1_#t~ite22, Thread2_P1_#t~ite20, ~z$r_buff0_thd2~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [556] L748-->L748-8: Formula: (and (not (= (mod v_~weak$$choice2~0_13 256) 0)) (= |v_Thread2_P1_#t~ite25_1| v_~z$r_buff1_thd2~0_16)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} OutVars{Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_16} AuxVars[] AssignedVars[Thread2_P1_#t~ite25] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [561] L748-8-->L750: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_3) (= v_~z$r_buff1_thd2~0_5 |v_Thread2_P1_#t~ite25_2|)) InVars {Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_2|, ~z~0=v_~z~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_5, Thread2_P1_#t~ite25=|v_Thread2_P1_#t~ite25_3|, Thread2_P1_#t~ite23=|v_Thread2_P1_#t~ite23_1|, Thread2_P1_#t~ite24=|v_Thread2_P1_#t~ite24_1|, ~z~0=v_~z~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, ~z$r_buff1_thd2~0, Thread2_P1_#t~ite25, Thread2_P1_#t~ite23, Thread2_P1_#t~ite24] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [565] L750-->L750-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread2_P1_#t~ite26_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_1|, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} AuxVars[] AssignedVars[Thread2_P1_#t~ite26] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |Thread2_P1_#t~ite26|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 [570] L750-2-->L758: Formula: (and (= v_~z~0_6 |v_Thread2_P1_#t~ite26_3|) (= v_~z$flush_delayed~0_4 0) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{Thread2_P1_#t~ite26=|v_Thread2_P1_#t~ite26_4|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread2_P1_#t~ite26, ~__unbuffered_cnt~0, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [336] L811-1-->L815: Formula: (= v_~main$tmp_guard0~0_1 (ite (= (ite (= v_~__unbuffered_cnt~0_7 3) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7} OutVars{ULTIMATE.start_main_#t~nondet37=|v_ULTIMATE.start_main_#t~nondet37_1|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_7, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet37, ~main$tmp_guard0~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [444] L815-->L817: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_2 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L817-->L817-2: Formula: (or (= 0 (mod v_~z$w_buff0_used~0_45 256)) (= (mod v_~z$r_buff0_thd0~0_3 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_45, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [485] L817-2-->L817-4: Formula: (and (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd0~0_3 256) 0)) (= |v_ULTIMATE.start_main_#t~ite38_2| v_~z~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_2|, ~z~0=v_~z~0_9, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite38] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [475] L817-4-->L817-5: Formula: (= |v_ULTIMATE.start_main_#t~ite39_2| |v_ULTIMATE.start_main_#t~ite38_3|) InVars {ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} OutVars{ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_2|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [477] L817-5-->L818: Formula: (= v_~z~0_10 |v_ULTIMATE.start_main_#t~ite39_4|) InVars {ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} OutVars{ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ~z~0=v_~z~0_10, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38, ~z~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [412] L818-->L818-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_5 256) 0) (= (mod v_~z$w_buff0_used~0_47 256) 0)) (= |v_ULTIMATE.start_main_#t~ite40_2| v_~z$w_buff0_used~0_47)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_47, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_5, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L818-2-->L819: Formula: (= v_~z$w_buff0_used~0_48 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ~z$w_buff0_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [341] L819-->L819-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite41_2| v_~z$w_buff1_used~0_28) (or (= 0 (mod v_~z$w_buff0_used~0_50 256)) (= 0 (mod v_~z$r_buff0_thd0~0_7 256))) (or (= (mod v_~z$r_buff1_thd0~0_5 256) 0) (= (mod v_~z$w_buff1_used~0_28 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_28, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_2|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_7, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [345] L819-2-->L820: Formula: (= v_~z$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite41_4|) InVars {ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$w_buff1_used~0] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [453] L820-->L820-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_2| v_~z$r_buff0_thd0~0_9) (or (= 0 (mod v_~z$r_buff0_thd0~0_9 256)) (= 0 (mod v_~z$w_buff0_used~0_52 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_52, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [459] L820-2-->L821: Formula: (= v_~z$r_buff0_thd0~0_10 |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L821-->L821-2: Formula: (and (or (= (mod v_~z$r_buff0_thd0~0_12 256) 0) (= 0 (mod v_~z$w_buff0_used~0_54 256))) (or (= (mod v_~z$r_buff1_thd0~0_7 256) 0) (= (mod v_~z$w_buff1_used~0_31 256) 0)) (= |v_ULTIMATE.start_main_#t~ite43_2| v_~z$r_buff1_thd0~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_31, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_12, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [388] L821-2-->L826: Formula: (and (= v_~z$r_buff1_thd0~0_8 |v_ULTIMATE.start_main_#t~ite43_4|) (= v_~main$tmp_guard1~0_1 (ite (= (ite (not (and (= 2 v_~x~0_3) (= v_~__unbuffered_p2_EBX~0_2 0) (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p2_EAX~0_2 1))) 1 0) 0) 0 1))) InVars {~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ~x~0=v_~x~0_3} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_2, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite43] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [443] L826-->L826-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [421] L826-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [379] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [375] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [371] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P2___VERIFIER_assert_~expression=1, Thread0_P2_thidvar0=2, Thread0_P2_~arg.base=0, Thread0_P2_~arg.offset=0, Thread1_P0_thidvar0=0, Thread1_P0_~arg.base=0, Thread1_P0_~arg.offset=0, Thread2_P1_thidvar0=1, Thread2_P1_~arg.base=0, Thread2_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P2_#in~arg.base|=0, |Thread0_P2_#in~arg.offset|=0, |Thread0_P2___VERIFIER_assert_#in~expression|=1, |Thread1_P0_#in~arg.base|=0, |Thread1_P0_#in~arg.offset|=0, |Thread2_P1_#in~arg.base|=0, |Thread2_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [?] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [?] -1 ~a~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [?] -1 ~b~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd3~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); srcloc: L806 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); srcloc: L806-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); srcloc: L808 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); srcloc: L808-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet36; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); srcloc: L810 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); srcloc: L810-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 2 P2(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0;~z$r_buff0_thd3~0 := 1;~a~0 := 1;~__unbuffered_p2_EAX~0 := ~a~0;~__unbuffered_p2_EBX~0 := ~b~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite29 := ~z$w_buff0~0; VAL [P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~b~0 := 1;~x~0 := 1;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 2;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1);havoc #t~nondet4.base, #t~nondet4.offset;~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1);havoc #t~nondet5.base, #t~nondet5.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite7 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite29|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite29;havoc #t~ite29;havoc #t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256;#t~ite30 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite30|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite30;havoc #t~ite30; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite31 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite31|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite31;havoc #t~ite31; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256);#t~ite32 := ~z$r_buff0_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite32|=1, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd3~0 := #t~ite32;havoc #t~ite32; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256));#t~ite33 := ~z$r_buff1_thd3~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2_#t~ite33|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd3~0 := #t~ite33;havoc #t~ite33;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite7|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 2 ~z~0 := #t~ite7;havoc #t~ite7;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite10 := ~z$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite10|=1, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0~0 := #t~ite10;havoc #t~ite9;havoc #t~ite10;havoc #t~ite8; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite13 := ~z$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1~0 := #t~ite13;havoc #t~ite13;havoc #t~ite12;havoc #t~ite11; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff0_used~0 := #t~ite16;havoc #t~ite14;havoc #t~ite15;havoc #t~ite16; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$w_buff1_used~0 := #t~ite19;havoc #t~ite19;havoc #t~ite18;havoc #t~ite17; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff0_thd2~0 := #t~ite22;havoc #t~ite22;havoc #t~ite21;havoc #t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z$r_buff1_thd2~0 := #t~ite25;havoc #t~ite24;havoc #t~ite25;havoc #t~ite23;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 assume 0 != ~z$flush_delayed~0 % 256;#t~ite26 := ~z$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite26|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 2 ~z~0 := #t~ite26;havoc #t~ite26;~z$flush_delayed~0 := 0;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet37;~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite38 := ~z~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite39 := main_#t~ite38; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite38|=0, |ULTIMATE.start_main_#t~ite39|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite39;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite40 := ~z$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite40;havoc main_#t~ite40; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite41 := ~z$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite41|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite41;havoc main_#t~ite41; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite42;havoc main_#t~ite42; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite43;havoc main_#t~ite43;~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, P2___VERIFIER_assert_~expression=1, P2_~arg.base=0, P2_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P2_#in~arg.base|=0, |P2_#in~arg.offset|=0, |P2___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t884~0.base|=5, |ULTIMATE.start_main_~#t884~0.offset|=0, |ULTIMATE.start_main_~#t885~0.base|=7, |ULTIMATE.start_main_~#t885~0.offset|=0, |ULTIMATE.start_main_~#t886~0.base|=6, |ULTIMATE.start_main_~#t886~0.offset|=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0.base, main_~#t884~0.offset, main_~#t885~0.base, main_~#t885~0.offset, main_~#t886~0.base, main_~#t886~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] -1 call main_~#t884~0.base, main_~#t884~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 call write~int(0, main_~#t884~0.base, main_~#t884~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] -1 call main_~#t885~0.base, main_~#t885~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 call write~int(1, main_~#t885~0.base, main_~#t885~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] -1 call main_~#t886~0.base, main_~#t886~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 call write~int(2, main_~#t886~0.base, main_~#t886~0.offset, 4); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4.base + #t~nondet4.offset then 0 else 1); [L738] 2 havoc #t~nondet4.base, #t~nondet4.offset; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5.base + #t~nondet5.offset then 0 else 1); [L739] 2 havoc #t~nondet5.base, #t~nondet5.offset; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] 2 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256; [L785] 0 #t~ite30 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256); [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)); [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 assume 0 != ~weak$$choice2~0 % 256; [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 assume 0 != ~weak$$choice2~0 % 256; [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 assume 0 != ~weak$$choice2~0 % 256; [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 assume 0 != ~weak$$choice2~0 % 256; [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 assume 0 != ~weak$$choice2~0 % 256; [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 assume 0 != ~weak$$choice2~0 % 256; [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 assume 0 != ~z$flush_delayed~0 % 256; [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0.base=5, main_~#t884~0.offset=0, main_~#t885~0.base=7, main_~#t885~0.offset=0, main_~#t886~0.base=6, main_~#t886~0.offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~arg.offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0, main_~#t885~0, main_~#t886~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet35, main_#t~nondet36, main_#t~nondet37, main_#t~ite39, main_#t~ite38, main_#t~ite40, main_#t~ite41, main_#t~ite42, main_#t~ite43, main_~#t884~0, main_~#t885~0, main_~#t886~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call main_~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, main_~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc main_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call main_~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, main_~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc main_#t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call main_~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, main_~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L767] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L767] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite29=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite30=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=1, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc main_#t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 main_#t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 main_#t~ite39 := main_#t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite38=0, main_#t~ite39=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := main_#t~ite39; [L817] -1 havoc main_#t~ite38; [L817] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 main_#t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := main_#t~ite40; [L818] -1 havoc main_#t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 main_#t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite41=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := main_#t~ite41; [L819] -1 havoc main_#t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 main_#t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := main_#t~ite42; [L820] -1 havoc main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 main_#t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := main_#t~ite43; [L821] -1 havoc main_#t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L826] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, __VERIFIER_assert_~expression=0, main_~#t884~0!base=5, main_~#t884~0!offset=0, main_~#t885~0!base=7, main_~#t885~0!offset=0, main_~#t886~0!base=6, main_~#t886~0!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L672] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L674] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L676] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~__unbuffered_p2_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0] [L680] -1 ~__unbuffered_p2_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0] [L682] -1 ~a~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0] [L684] -1 ~b~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0] [L685] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0] [L686] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L688] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L690] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L692] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L693] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L694] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L695] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L696] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L697] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L698] -1 ~z$r_buff0_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z~0=0] [L699] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L700] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L701] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L702] -1 ~z$r_buff1_thd3~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z~0=0] [L703] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed~0=0, ~z~0=0] [L704] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L705] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L706] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L707] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L708] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L709] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L806] FCALL -1 call ~#t884~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FCALL -1 call write~int(0, ~#t884~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L807] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L808] FCALL -1 call ~#t885~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FCALL -1 call write~int(1, ~#t885~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L809] -1 havoc #t~nondet36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L810] FCALL -1 call ~#t886~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FCALL -1 call write~int(2, ~#t886~0, 4); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] FORK -1 fork 2 P2({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760-L794] 0 ~arg := #in~arg; [L763] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L764] 0 ~z$w_buff0~0 := 1; [L765] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L766] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=0, ~__unbuffered_p2_EBX~0=0, ~a~0=0, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L768] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L769] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L770] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L771] 0 ~z$r_buff1_thd3~0 := ~z$r_buff0_thd3~0; [L772] 0 ~z$r_buff0_thd3~0 := 1; [L775] 0 ~a~0 := 1; [L778] 0 ~__unbuffered_p2_EAX~0 := ~a~0; [L781] 0 ~__unbuffered_p2_EBX~0 := ~b~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L784] 0 #t~ite29 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~a~0=1, ~b~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L711-L725] 1 ~arg := #in~arg; [L714] 1 ~b~0 := 1; [L717] 1 ~x~0 := 1; [L722] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=1, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L726-L759] 2 ~arg := #in~arg; [L729] 2 ~x~0 := 2; [L732] 2 ~y~0 := 1; [L735] 2 ~__unbuffered_p1_EAX~0 := ~y~0; [L738] 2 ~weak$$choice0~0 := (if 0 == #t~nondet4!base + #t~nondet4!offset then 0 else 1); [L738] 2 havoc #t~nondet4; [L739] 2 ~weak$$choice2~0 := (if 0 == #t~nondet5!base + #t~nondet5!offset then 0 else 1); [L739] 2 havoc #t~nondet5; [L740] 2 ~z$flush_delayed~0 := ~weak$$choice2~0; [L741] 2 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L742] COND TRUE 2 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L742] 2 #t~ite7 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L784] 0 ~z~0 := #t~ite29; [L784] 0 havoc #t~ite29; [L784] 0 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256 [L785] 0 #t~ite30 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L785] 0 ~z$w_buff0_used~0 := #t~ite30; [L785] 0 havoc #t~ite30; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L786] 0 #t~ite31 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L786] 0 ~z$w_buff1_used~0 := #t~ite31; [L786] 0 havoc #t~ite31; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) [L787] 0 #t~ite32 := ~z$r_buff0_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L787] 0 ~z$r_buff0_thd3~0 := #t~ite32; [L787] 0 havoc #t~ite32; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd3~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd3~0 % 256)) [L788] 0 #t~ite33 := ~z$r_buff1_thd3~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L788] 0 ~z$r_buff1_thd3~0 := #t~ite33; [L788] 0 havoc #t~ite33; [L791] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L742] 2 ~z~0 := #t~ite7; [L742] 2 havoc #t~ite7; [L742] 2 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L743] 2 #t~ite10 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite10=1, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L743] 2 ~z$w_buff0~0 := #t~ite10; [L743] 2 havoc #t~ite9; [L743] 2 havoc #t~ite10; [L743] 2 havoc #t~ite8; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L744] 2 #t~ite13 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L744] 2 ~z$w_buff1~0 := #t~ite13; [L744] 2 havoc #t~ite13; [L744] 2 havoc #t~ite12; [L744] 2 havoc #t~ite11; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L745] 2 #t~ite16 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L745] 2 ~z$w_buff0_used~0 := #t~ite16; [L745] 2 havoc #t~ite14; [L745] 2 havoc #t~ite15; [L745] 2 havoc #t~ite16; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L746] 2 #t~ite19 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 2 ~z$w_buff1_used~0 := #t~ite19; [L746] 2 havoc #t~ite19; [L746] 2 havoc #t~ite18; [L746] 2 havoc #t~ite17; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L747] 2 #t~ite22 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 2 ~z$r_buff0_thd2~0 := #t~ite22; [L747] 2 havoc #t~ite22; [L747] 2 havoc #t~ite21; [L747] 2 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 2 0 != ~weak$$choice2~0 % 256 [L748] 2 #t~ite25 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 2 ~z$r_buff1_thd2~0 := #t~ite25; [L748] 2 havoc #t~ite24; [L748] 2 havoc #t~ite25; [L748] 2 havoc #t~ite23; [L749] 2 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 2 0 != ~z$flush_delayed~0 % 256 [L750] 2 #t~ite26 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite26=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 2 ~z~0 := #t~ite26; [L750] 2 havoc #t~ite26; [L751] 2 ~z$flush_delayed~0 := 0; [L756] 2 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L811] -1 havoc #t~nondet37; [L813] -1 ~main$tmp_guard0~0 := (if 0 == (if 3 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L815] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L817] -1 #t~ite38 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 #t~ite39 := #t~ite38; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L817] -1 ~z~0 := #t~ite39; [L817] -1 havoc #t~ite38; [L817] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L818] -1 #t~ite40 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L818] -1 ~z$w_buff0_used~0 := #t~ite40; [L818] -1 havoc #t~ite40; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L819] -1 #t~ite41 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L819] -1 ~z$w_buff1_used~0 := #t~ite41; [L819] -1 havoc #t~ite41; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L820] -1 #t~ite42 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L820] -1 ~z$r_buff0_thd0~0 := #t~ite42; [L820] -1 havoc #t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L821] -1 #t~ite43 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L821] -1 ~z$r_buff1_thd0~0 := #t~ite43; [L821] -1 havoc #t~ite43; [L824] -1 ~main$tmp_guard1~0 := (if 0 == (if !((((2 == ~x~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) && 1 == ~__unbuffered_p2_EAX~0) && 0 == ~__unbuffered_p2_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=3, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~__unbuffered_p2_EAX~0=1, ~__unbuffered_p2_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~a~0=1, ~b~0=1, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=1, ~weak$$choice2~0=1, ~x~0=2, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff0_thd3~0=1, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$r_buff1_thd3~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t884; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t884, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t885; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t885, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t886; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t886, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-23 07:20:49,181 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_c78b618e-66e3-4d1b-a4ea-1e413bd52987/bin-2019/utaipan/witness.graphml [2018-11-23 07:20:49,181 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 07:20:49,182 INFO L168 Benchmark]: Toolchain (without parser) took 76058.67 ms. Allocated memory was 1.0 GB in the beginning and 6.5 GB in the end (delta: 5.5 GB). Free memory was 956.4 MB in the beginning and 3.4 GB in the end (delta: -2.5 GB). Peak memory consumption was 3.0 GB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,183 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:20:49,183 INFO L168 Benchmark]: CACSL2BoogieTranslator took 404.54 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -177.0 MB). Peak memory consumption was 38.2 MB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,183 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,184 INFO L168 Benchmark]: Boogie Preprocessor took 27.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,184 INFO L168 Benchmark]: RCFGBuilder took 515.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.7 MB). Peak memory consumption was 51.7 MB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,184 INFO L168 Benchmark]: TraceAbstraction took 70058.04 ms. Allocated memory was 1.2 GB in the beginning and 6.5 GB in the end (delta: 5.3 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 2.8 GB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,184 INFO L168 Benchmark]: Witness Printer took 5008.24 ms. Allocated memory is still 6.5 GB. Free memory was 3.6 GB in the beginning and 3.4 GB in the end (delta: 152.9 MB). Peak memory consumption was 152.9 MB. Max. memory is 11.5 GB. [2018-11-23 07:20:49,186 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 404.54 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 156.8 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -177.0 MB). Peak memory consumption was 38.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 515.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.7 MB). Peak memory consumption was 51.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 70058.04 ms. Allocated memory was 1.2 GB in the beginning and 6.5 GB in the end (delta: 5.3 GB). Free memory was 1.1 GB in the beginning and 3.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 2.8 GB. Max. memory is 11.5 GB. * Witness Printer took 5008.24 ms. Allocated memory is still 6.5 GB. Free memory was 3.6 GB in the beginning and 3.4 GB in the end (delta: 152.9 MB). Peak memory consumption was 152.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L672] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L674] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L676] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0] [L680] -1 int __unbuffered_p2_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0] [L682] -1 int a = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0] [L684] -1 int b = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0] [L685] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0] [L686] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0] [L688] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L690] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L692] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L693] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L694] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L695] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L696] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L697] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L698] -1 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L699] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L700] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L701] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L702] -1 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L703] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L704] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L705] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L706] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L707] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L708] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L709] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L710] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L806] -1 pthread_t t884; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L807] FCALL, FORK -1 pthread_create(&t884, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L808] -1 pthread_t t885; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L809] FCALL, FORK -1 pthread_create(&t885, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L810] -1 pthread_t t886; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L811] FCALL, FORK -1 pthread_create(&t886, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 0 z$w_buff1 = z$w_buff0 [L764] 0 z$w_buff0 = 1 [L765] 0 z$w_buff1_used = z$w_buff0_used [L766] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L769] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L770] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L771] 0 z$r_buff1_thd3 = z$r_buff0_thd3 [L772] 0 z$r_buff0_thd3 = (_Bool)1 [L775] 0 a = 1 [L778] 0 __unbuffered_p2_EAX = a [L781] 0 __unbuffered_p2_EBX = b VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, b=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L714] 1 b = 1 [L717] 1 x = 1 [L722] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L729] 2 x = 2 [L732] 2 y = 1 [L735] 2 __unbuffered_p1_EAX = y [L738] 2 weak$$choice0 = __VERIFIER_nondet_pointer() [L739] 2 weak$$choice2 = __VERIFIER_nondet_pointer() [L740] 2 z$flush_delayed = weak$$choice2 [L741] 2 z$mem_tmp = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L742] EXPR 2 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L784] 0 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L785] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L785] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L786] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L786] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L787] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 0 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L788] EXPR 0 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=1, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L788] 0 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L791] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L742] 2 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L743] EXPR 2 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 2 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L744] EXPR 2 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 2 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L745] EXPR 2 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 2 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L746] EXPR 2 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L746] 2 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L747] EXPR 2 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L747] 2 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L748] EXPR 2 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L748] 2 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L749] 2 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] EXPR 2 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L750] 2 z = z$flush_delayed ? z$mem_tmp : z [L751] 2 z$flush_delayed = (_Bool)0 [L756] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L813] -1 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L817] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L818] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L818] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L819] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L819] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L820] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L820] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L821] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L821] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L824] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, b=1, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=1, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 221 locations, 3 error locations. UNSAFE Result, 69.9s OverallTime, 24 OverallIterations, 1 TraceHistogramMax, 17.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 6552 SDtfs, 8160 SDslu, 15193 SDs, 0 SdLazy, 5303 SolverSat, 288 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 226 GetRequests, 61 SyntacticMatches, 16 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 126 ImplicationChecksByTransitivity, 1.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=149047occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 24.9s AutomataMinimizationTime, 23 MinimizatonAttempts, 210379 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.4s InterpolantComputationTime, 1840 NumberOfCodeBlocks, 1840 NumberOfCodeBlocksAsserted, 24 NumberOfCheckSat, 1722 ConstructedInterpolants, 0 QuantifiedInterpolants, 322023 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 23 InterpolantComputations, 23 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...