./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix034_rmo.oepc_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix034_rmo.oepc_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4a052330b4479085cb8bf5435fb8596eeb294355 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 23:46:56,843 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 23:46:56,844 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 23:46:56,850 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 23:46:56,851 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 23:46:56,851 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 23:46:56,852 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 23:46:56,853 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 23:46:56,854 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 23:46:56,855 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 23:46:56,856 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 23:46:56,856 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 23:46:56,856 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 23:46:56,857 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 23:46:56,857 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 23:46:56,858 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 23:46:56,858 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 23:46:56,859 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 23:46:56,860 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 23:46:56,861 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 23:46:56,862 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 23:46:56,862 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 23:46:56,864 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 23:46:56,864 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 23:46:56,864 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 23:46:56,865 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 23:46:56,865 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 23:46:56,866 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 23:46:56,866 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 23:46:56,867 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 23:46:56,867 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 23:46:56,868 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 23:46:56,868 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 23:46:56,868 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 23:46:56,869 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 23:46:56,869 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 23:46:56,869 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-22 23:46:56,877 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 23:46:56,878 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 23:46:56,878 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 23:46:56,878 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-22 23:46:56,879 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-22 23:46:56,879 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-22 23:46:56,880 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-22 23:46:56,880 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 23:46:56,880 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-22 23:46:56,880 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 23:46:56,880 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 23:46:56,881 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 23:46:56,882 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 23:46:56,882 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 23:46:56,882 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 23:46:56,882 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 23:46:56,882 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 23:46:56,882 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 23:46:56,882 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-22 23:46:56,883 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4a052330b4479085cb8bf5435fb8596eeb294355 [2018-11-22 23:46:56,906 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 23:46:56,915 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 23:46:56,918 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 23:46:56,919 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 23:46:56,919 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 23:46:56,920 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/../../sv-benchmarks/c/pthread-wmm/mix034_rmo.oepc_false-unreach-call.i [2018-11-22 23:46:56,961 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/data/72ee5c72b/d035c9cc16a4439f8291cba981391bfb/FLAG8fe47fb01 [2018-11-22 23:46:57,296 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 23:46:57,296 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/sv-benchmarks/c/pthread-wmm/mix034_rmo.oepc_false-unreach-call.i [2018-11-22 23:46:57,304 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/data/72ee5c72b/d035c9cc16a4439f8291cba981391bfb/FLAG8fe47fb01 [2018-11-22 23:46:57,313 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/data/72ee5c72b/d035c9cc16a4439f8291cba981391bfb [2018-11-22 23:46:57,315 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 23:46:57,316 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 23:46:57,316 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 23:46:57,317 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 23:46:57,319 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 23:46:57,319 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,321 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e1fb88e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57, skipping insertion in model container [2018-11-22 23:46:57,321 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,327 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 23:46:57,356 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 23:46:57,587 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 23:46:57,595 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 23:46:57,684 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 23:46:57,729 INFO L195 MainTranslator]: Completed translation [2018-11-22 23:46:57,729 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57 WrapperNode [2018-11-22 23:46:57,729 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 23:46:57,730 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 23:46:57,730 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 23:46:57,730 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 23:46:57,737 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,750 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,769 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 23:46:57,770 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 23:46:57,770 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 23:46:57,770 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 23:46:57,778 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,778 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,781 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,781 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,788 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,791 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,793 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... [2018-11-22 23:46:57,796 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 23:46:57,797 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 23:46:57,797 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 23:46:57,797 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 23:46:57,797 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 23:46:57,848 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-22 23:46:57,848 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-22 23:46:57,848 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-22 23:46:57,848 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-22 23:46:57,849 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-22 23:46:57,849 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-22 23:46:57,849 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-22 23:46:57,849 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-22 23:46:57,849 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-22 23:46:57,849 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 23:46:57,849 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 23:46:57,850 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-22 23:46:58,321 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 23:46:58,321 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-22 23:46:58,321 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:46:58 BoogieIcfgContainer [2018-11-22 23:46:58,321 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 23:46:58,322 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 23:46:58,322 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 23:46:58,323 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 23:46:58,324 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 11:46:57" (1/3) ... [2018-11-22 23:46:58,324 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24453e40 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 11:46:58, skipping insertion in model container [2018-11-22 23:46:58,324 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:46:57" (2/3) ... [2018-11-22 23:46:58,324 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24453e40 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 11:46:58, skipping insertion in model container [2018-11-22 23:46:58,324 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:46:58" (3/3) ... [2018-11-22 23:46:58,325 INFO L112 eAbstractionObserver]: Analyzing ICFG mix034_rmo.oepc_false-unreach-call.i [2018-11-22 23:46:58,349 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,350 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,351 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,352 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,353 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,354 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,355 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,355 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,355 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,355 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,356 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet11.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet10.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,357 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,358 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,359 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,360 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,361 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,362 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,363 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,364 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,365 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,366 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,367 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,368 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,369 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,369 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,369 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,373 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,374 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,375 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,376 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,376 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,376 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,376 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,376 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet39.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-22 23:46:58,390 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-22 23:46:58,390 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 23:46:58,395 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-22 23:46:58,405 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-22 23:46:58,423 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 23:46:58,424 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 23:46:58,424 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 23:46:58,424 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 23:46:58,424 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 23:46:58,424 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 23:46:58,424 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 23:46:58,424 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 23:46:58,433 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 144places, 182 transitions [2018-11-22 23:46:59,956 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 34808 states. [2018-11-22 23:46:59,957 INFO L276 IsEmpty]: Start isEmpty. Operand 34808 states. [2018-11-22 23:46:59,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-11-22 23:46:59,964 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:46:59,964 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:46:59,965 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:46:59,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:46:59,969 INFO L82 PathProgramCache]: Analyzing trace with hash 998748630, now seen corresponding path program 1 times [2018-11-22 23:46:59,970 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:00,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:00,006 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:00,006 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:00,006 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:00,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:00,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:00,141 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:00,142 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:00,142 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:00,146 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:00,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:00,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:00,160 INFO L87 Difference]: Start difference. First operand 34808 states. Second operand 4 states. [2018-11-22 23:47:00,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:00,894 INFO L93 Difference]: Finished difference Result 60792 states and 234495 transitions. [2018-11-22 23:47:00,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 23:47:00,896 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2018-11-22 23:47:00,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:01,049 INFO L225 Difference]: With dead ends: 60792 [2018-11-22 23:47:01,049 INFO L226 Difference]: Without dead ends: 44272 [2018-11-22 23:47:01,051 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:01,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44272 states. [2018-11-22 23:47:01,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44272 to 27340. [2018-11-22 23:47:01,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27340 states. [2018-11-22 23:47:01,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27340 states to 27340 states and 105501 transitions. [2018-11-22 23:47:01,944 INFO L78 Accepts]: Start accepts. Automaton has 27340 states and 105501 transitions. Word has length 35 [2018-11-22 23:47:01,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:01,945 INFO L480 AbstractCegarLoop]: Abstraction has 27340 states and 105501 transitions. [2018-11-22 23:47:01,945 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:01,945 INFO L276 IsEmpty]: Start isEmpty. Operand 27340 states and 105501 transitions. [2018-11-22 23:47:01,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-22 23:47:01,952 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:01,952 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:01,952 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:01,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:01,952 INFO L82 PathProgramCache]: Analyzing trace with hash 1553228635, now seen corresponding path program 1 times [2018-11-22 23:47:01,952 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:01,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:01,956 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:01,956 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:01,956 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:01,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:02,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:02,031 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:02,031 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:02,031 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:02,032 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:02,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:02,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:02,033 INFO L87 Difference]: Start difference. First operand 27340 states and 105501 transitions. Second operand 4 states. [2018-11-22 23:47:02,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:02,151 INFO L93 Difference]: Finished difference Result 8530 states and 28346 transitions. [2018-11-22 23:47:02,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 23:47:02,152 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 47 [2018-11-22 23:47:02,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:02,180 INFO L225 Difference]: With dead ends: 8530 [2018-11-22 23:47:02,180 INFO L226 Difference]: Without dead ends: 7468 [2018-11-22 23:47:02,181 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:02,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7468 states. [2018-11-22 23:47:02,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7468 to 7468. [2018-11-22 23:47:02,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7468 states. [2018-11-22 23:47:02,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7468 states to 7468 states and 24638 transitions. [2018-11-22 23:47:02,305 INFO L78 Accepts]: Start accepts. Automaton has 7468 states and 24638 transitions. Word has length 47 [2018-11-22 23:47:02,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:02,305 INFO L480 AbstractCegarLoop]: Abstraction has 7468 states and 24638 transitions. [2018-11-22 23:47:02,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:02,305 INFO L276 IsEmpty]: Start isEmpty. Operand 7468 states and 24638 transitions. [2018-11-22 23:47:02,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-22 23:47:02,306 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:02,306 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:02,307 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:02,307 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:02,307 INFO L82 PathProgramCache]: Analyzing trace with hash -508045602, now seen corresponding path program 1 times [2018-11-22 23:47:02,307 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:02,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:02,309 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:02,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:02,310 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:02,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:02,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:02,407 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:02,407 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:02,407 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:02,407 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:02,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:02,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:02,408 INFO L87 Difference]: Start difference. First operand 7468 states and 24638 transitions. Second operand 6 states. [2018-11-22 23:47:02,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:02,823 INFO L93 Difference]: Finished difference Result 9664 states and 31135 transitions. [2018-11-22 23:47:02,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 23:47:02,823 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-11-22 23:47:02,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:02,839 INFO L225 Difference]: With dead ends: 9664 [2018-11-22 23:47:02,839 INFO L226 Difference]: Without dead ends: 9596 [2018-11-22 23:47:02,839 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2018-11-22 23:47:02,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9596 states. [2018-11-22 23:47:03,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9596 to 9443. [2018-11-22 23:47:03,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9443 states. [2018-11-22 23:47:03,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9443 states to 9443 states and 30544 transitions. [2018-11-22 23:47:03,044 INFO L78 Accepts]: Start accepts. Automaton has 9443 states and 30544 transitions. Word has length 48 [2018-11-22 23:47:03,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:03,045 INFO L480 AbstractCegarLoop]: Abstraction has 9443 states and 30544 transitions. [2018-11-22 23:47:03,045 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:03,045 INFO L276 IsEmpty]: Start isEmpty. Operand 9443 states and 30544 transitions. [2018-11-22 23:47:03,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 23:47:03,046 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:03,046 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:03,046 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:03,047 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:03,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1928335132, now seen corresponding path program 1 times [2018-11-22 23:47:03,047 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:03,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,049 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:03,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,049 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:03,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:03,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:03,086 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:03,086 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:47:03,086 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:03,087 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:47:03,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:47:03,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:03,087 INFO L87 Difference]: Start difference. First operand 9443 states and 30544 transitions. Second operand 3 states. [2018-11-22 23:47:03,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:03,143 INFO L93 Difference]: Finished difference Result 13281 states and 42643 transitions. [2018-11-22 23:47:03,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:47:03,144 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 50 [2018-11-22 23:47:03,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:03,161 INFO L225 Difference]: With dead ends: 13281 [2018-11-22 23:47:03,161 INFO L226 Difference]: Without dead ends: 13281 [2018-11-22 23:47:03,161 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:03,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13281 states. [2018-11-22 23:47:03,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13281 to 9847. [2018-11-22 23:47:03,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9847 states. [2018-11-22 23:47:03,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9847 states to 9847 states and 31510 transitions. [2018-11-22 23:47:03,282 INFO L78 Accepts]: Start accepts. Automaton has 9847 states and 31510 transitions. Word has length 50 [2018-11-22 23:47:03,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:03,283 INFO L480 AbstractCegarLoop]: Abstraction has 9847 states and 31510 transitions. [2018-11-22 23:47:03,283 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:47:03,283 INFO L276 IsEmpty]: Start isEmpty. Operand 9847 states and 31510 transitions. [2018-11-22 23:47:03,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-11-22 23:47:03,284 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:03,284 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:03,284 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:03,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:03,285 INFO L82 PathProgramCache]: Analyzing trace with hash 1510963439, now seen corresponding path program 1 times [2018-11-22 23:47:03,285 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:03,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,286 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:03,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,287 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:03,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:03,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:03,356 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:03,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:03,356 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:03,356 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:03,357 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:03,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:03,357 INFO L87 Difference]: Start difference. First operand 9847 states and 31510 transitions. Second operand 6 states. [2018-11-22 23:47:03,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:03,676 INFO L93 Difference]: Finished difference Result 14205 states and 45066 transitions. [2018-11-22 23:47:03,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 23:47:03,677 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 54 [2018-11-22 23:47:03,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:03,694 INFO L225 Difference]: With dead ends: 14205 [2018-11-22 23:47:03,695 INFO L226 Difference]: Without dead ends: 14133 [2018-11-22 23:47:03,695 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-11-22 23:47:03,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14133 states. [2018-11-22 23:47:03,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14133 to 10851. [2018-11-22 23:47:03,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10851 states. [2018-11-22 23:47:03,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10851 states to 10851 states and 34565 transitions. [2018-11-22 23:47:03,825 INFO L78 Accepts]: Start accepts. Automaton has 10851 states and 34565 transitions. Word has length 54 [2018-11-22 23:47:03,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:03,826 INFO L480 AbstractCegarLoop]: Abstraction has 10851 states and 34565 transitions. [2018-11-22 23:47:03,826 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:03,826 INFO L276 IsEmpty]: Start isEmpty. Operand 10851 states and 34565 transitions. [2018-11-22 23:47:03,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-22 23:47:03,829 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:03,829 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:03,829 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:03,829 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:03,829 INFO L82 PathProgramCache]: Analyzing trace with hash 516780875, now seen corresponding path program 1 times [2018-11-22 23:47:03,830 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:03,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,831 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:03,831 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:03,831 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:03,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:03,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:03,890 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:03,890 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:03,890 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:03,890 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:03,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:03,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:03,891 INFO L87 Difference]: Start difference. First operand 10851 states and 34565 transitions. Second operand 4 states. [2018-11-22 23:47:03,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:03,978 INFO L93 Difference]: Finished difference Result 12398 states and 39574 transitions. [2018-11-22 23:47:03,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 23:47:03,978 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 62 [2018-11-22 23:47:03,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:03,992 INFO L225 Difference]: With dead ends: 12398 [2018-11-22 23:47:03,993 INFO L226 Difference]: Without dead ends: 12398 [2018-11-22 23:47:03,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:04,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12398 states. [2018-11-22 23:47:04,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12398 to 11371. [2018-11-22 23:47:04,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11371 states. [2018-11-22 23:47:04,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11371 states to 11371 states and 36238 transitions. [2018-11-22 23:47:04,178 INFO L78 Accepts]: Start accepts. Automaton has 11371 states and 36238 transitions. Word has length 62 [2018-11-22 23:47:04,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:04,179 INFO L480 AbstractCegarLoop]: Abstraction has 11371 states and 36238 transitions. [2018-11-22 23:47:04,179 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:04,179 INFO L276 IsEmpty]: Start isEmpty. Operand 11371 states and 36238 transitions. [2018-11-22 23:47:04,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-22 23:47:04,182 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:04,182 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:04,183 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:04,183 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:04,183 INFO L82 PathProgramCache]: Analyzing trace with hash -2035376086, now seen corresponding path program 1 times [2018-11-22 23:47:04,183 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:04,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:04,184 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:04,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:04,184 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:04,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:04,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:04,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:04,268 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:04,268 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:04,268 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:04,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:04,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:04,268 INFO L87 Difference]: Start difference. First operand 11371 states and 36238 transitions. Second operand 6 states. [2018-11-22 23:47:04,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:04,539 INFO L93 Difference]: Finished difference Result 20971 states and 66488 transitions. [2018-11-22 23:47:04,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-22 23:47:04,539 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 62 [2018-11-22 23:47:04,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:04,562 INFO L225 Difference]: With dead ends: 20971 [2018-11-22 23:47:04,562 INFO L226 Difference]: Without dead ends: 20900 [2018-11-22 23:47:04,563 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-11-22 23:47:04,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20900 states. [2018-11-22 23:47:04,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20900 to 13757. [2018-11-22 23:47:04,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13757 states. [2018-11-22 23:47:04,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13757 states to 13757 states and 43282 transitions. [2018-11-22 23:47:04,739 INFO L78 Accepts]: Start accepts. Automaton has 13757 states and 43282 transitions. Word has length 62 [2018-11-22 23:47:04,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:04,739 INFO L480 AbstractCegarLoop]: Abstraction has 13757 states and 43282 transitions. [2018-11-22 23:47:04,739 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:04,739 INFO L276 IsEmpty]: Start isEmpty. Operand 13757 states and 43282 transitions. [2018-11-22 23:47:04,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-22 23:47:04,744 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:04,744 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:04,745 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:04,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:04,745 INFO L82 PathProgramCache]: Analyzing trace with hash -1982350530, now seen corresponding path program 1 times [2018-11-22 23:47:04,745 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:04,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:04,747 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:04,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:04,747 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:04,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:04,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:04,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:04,811 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:04,811 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:04,811 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:04,812 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:04,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:04,812 INFO L87 Difference]: Start difference. First operand 13757 states and 43282 transitions. Second operand 4 states. [2018-11-22 23:47:05,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:05,005 INFO L93 Difference]: Finished difference Result 17637 states and 54587 transitions. [2018-11-22 23:47:05,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 23:47:05,005 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2018-11-22 23:47:05,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:05,026 INFO L225 Difference]: With dead ends: 17637 [2018-11-22 23:47:05,026 INFO L226 Difference]: Without dead ends: 17637 [2018-11-22 23:47:05,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:05,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17637 states. [2018-11-22 23:47:05,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17637 to 15795. [2018-11-22 23:47:05,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15795 states. [2018-11-22 23:47:05,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15795 states to 15795 states and 49133 transitions. [2018-11-22 23:47:05,210 INFO L78 Accepts]: Start accepts. Automaton has 15795 states and 49133 transitions. Word has length 66 [2018-11-22 23:47:05,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:05,211 INFO L480 AbstractCegarLoop]: Abstraction has 15795 states and 49133 transitions. [2018-11-22 23:47:05,211 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:05,211 INFO L276 IsEmpty]: Start isEmpty. Operand 15795 states and 49133 transitions. [2018-11-22 23:47:05,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-22 23:47:05,219 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:05,219 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:05,219 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:05,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:05,220 INFO L82 PathProgramCache]: Analyzing trace with hash 2057880221, now seen corresponding path program 1 times [2018-11-22 23:47:05,220 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:05,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:05,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:05,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:05,222 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:05,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:05,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:05,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:05,267 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:47:05,267 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:05,267 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:47:05,267 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:47:05,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:05,269 INFO L87 Difference]: Start difference. First operand 15795 states and 49133 transitions. Second operand 3 states. [2018-11-22 23:47:05,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:05,437 INFO L93 Difference]: Finished difference Result 16387 states and 50740 transitions. [2018-11-22 23:47:05,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:47:05,438 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2018-11-22 23:47:05,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:05,456 INFO L225 Difference]: With dead ends: 16387 [2018-11-22 23:47:05,456 INFO L226 Difference]: Without dead ends: 16387 [2018-11-22 23:47:05,457 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:05,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16387 states. [2018-11-22 23:47:05,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16387 to 16111. [2018-11-22 23:47:05,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16111 states. [2018-11-22 23:47:05,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16111 states to 16111 states and 49983 transitions. [2018-11-22 23:47:05,776 INFO L78 Accepts]: Start accepts. Automaton has 16111 states and 49983 transitions. Word has length 66 [2018-11-22 23:47:05,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:05,777 INFO L480 AbstractCegarLoop]: Abstraction has 16111 states and 49983 transitions. [2018-11-22 23:47:05,777 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:47:05,777 INFO L276 IsEmpty]: Start isEmpty. Operand 16111 states and 49983 transitions. [2018-11-22 23:47:05,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:05,782 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:05,782 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:05,782 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:05,783 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:05,783 INFO L82 PathProgramCache]: Analyzing trace with hash -356405788, now seen corresponding path program 1 times [2018-11-22 23:47:05,783 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:05,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:05,784 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:05,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:05,784 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:05,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:05,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:05,875 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:05,876 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:05,876 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:05,876 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:05,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:05,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:05,878 INFO L87 Difference]: Start difference. First operand 16111 states and 49983 transitions. Second operand 6 states. [2018-11-22 23:47:06,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:06,495 INFO L93 Difference]: Finished difference Result 19823 states and 60439 transitions. [2018-11-22 23:47:06,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:47:06,495 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2018-11-22 23:47:06,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:06,516 INFO L225 Difference]: With dead ends: 19823 [2018-11-22 23:47:06,516 INFO L226 Difference]: Without dead ends: 19823 [2018-11-22 23:47:06,516 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:06,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19823 states. [2018-11-22 23:47:06,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19823 to 18619. [2018-11-22 23:47:06,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18619 states. [2018-11-22 23:47:06,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18619 states to 18619 states and 57219 transitions. [2018-11-22 23:47:06,712 INFO L78 Accepts]: Start accepts. Automaton has 18619 states and 57219 transitions. Word has length 68 [2018-11-22 23:47:06,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:06,713 INFO L480 AbstractCegarLoop]: Abstraction has 18619 states and 57219 transitions. [2018-11-22 23:47:06,713 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:06,713 INFO L276 IsEmpty]: Start isEmpty. Operand 18619 states and 57219 transitions. [2018-11-22 23:47:06,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:06,719 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:06,719 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:06,720 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:06,720 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:06,720 INFO L82 PathProgramCache]: Analyzing trace with hash -611142333, now seen corresponding path program 1 times [2018-11-22 23:47:06,720 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:06,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:06,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:06,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:06,722 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:06,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:06,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:06,816 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:06,816 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:06,816 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:06,816 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:06,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:06,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:06,817 INFO L87 Difference]: Start difference. First operand 18619 states and 57219 transitions. Second operand 6 states. [2018-11-22 23:47:07,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:07,076 INFO L93 Difference]: Finished difference Result 21451 states and 63628 transitions. [2018-11-22 23:47:07,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 23:47:07,077 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2018-11-22 23:47:07,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:07,099 INFO L225 Difference]: With dead ends: 21451 [2018-11-22 23:47:07,100 INFO L226 Difference]: Without dead ends: 21451 [2018-11-22 23:47:07,100 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-22 23:47:07,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21451 states. [2018-11-22 23:47:07,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21451 to 19135. [2018-11-22 23:47:07,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19135 states. [2018-11-22 23:47:07,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19135 states to 19135 states and 57766 transitions. [2018-11-22 23:47:07,303 INFO L78 Accepts]: Start accepts. Automaton has 19135 states and 57766 transitions. Word has length 68 [2018-11-22 23:47:07,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:07,303 INFO L480 AbstractCegarLoop]: Abstraction has 19135 states and 57766 transitions. [2018-11-22 23:47:07,303 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:07,303 INFO L276 IsEmpty]: Start isEmpty. Operand 19135 states and 57766 transitions. [2018-11-22 23:47:07,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:07,310 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:07,310 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:07,310 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:07,310 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:07,310 INFO L82 PathProgramCache]: Analyzing trace with hash -678149086, now seen corresponding path program 1 times [2018-11-22 23:47:07,311 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:07,312 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:07,312 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:07,312 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:07,312 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:07,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:07,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:07,376 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:07,376 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:07,376 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:07,376 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:07,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:07,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:07,376 INFO L87 Difference]: Start difference. First operand 19135 states and 57766 transitions. Second operand 5 states. [2018-11-22 23:47:07,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:07,633 INFO L93 Difference]: Finished difference Result 25026 states and 75020 transitions. [2018-11-22 23:47:07,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:47:07,634 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2018-11-22 23:47:07,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:07,661 INFO L225 Difference]: With dead ends: 25026 [2018-11-22 23:47:07,661 INFO L226 Difference]: Without dead ends: 25026 [2018-11-22 23:47:07,662 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:07,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25026 states. [2018-11-22 23:47:07,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25026 to 22711. [2018-11-22 23:47:07,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22711 states. [2018-11-22 23:47:07,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22711 states to 22711 states and 68034 transitions. [2018-11-22 23:47:07,956 INFO L78 Accepts]: Start accepts. Automaton has 22711 states and 68034 transitions. Word has length 68 [2018-11-22 23:47:07,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:07,956 INFO L480 AbstractCegarLoop]: Abstraction has 22711 states and 68034 transitions. [2018-11-22 23:47:07,956 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:07,956 INFO L276 IsEmpty]: Start isEmpty. Operand 22711 states and 68034 transitions. [2018-11-22 23:47:07,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:07,964 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:07,964 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:07,964 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:07,964 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:07,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1188683263, now seen corresponding path program 1 times [2018-11-22 23:47:07,964 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:07,965 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:07,965 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:07,966 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:07,966 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:07,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:08,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:08,032 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:08,032 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:08,032 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:08,032 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:08,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:08,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:08,033 INFO L87 Difference]: Start difference. First operand 22711 states and 68034 transitions. Second operand 5 states. [2018-11-22 23:47:08,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:08,324 INFO L93 Difference]: Finished difference Result 31961 states and 94873 transitions. [2018-11-22 23:47:08,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 23:47:08,324 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2018-11-22 23:47:08,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:08,360 INFO L225 Difference]: With dead ends: 31961 [2018-11-22 23:47:08,360 INFO L226 Difference]: Without dead ends: 31961 [2018-11-22 23:47:08,360 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:47:08,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31961 states. [2018-11-22 23:47:08,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31961 to 28241. [2018-11-22 23:47:08,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28241 states. [2018-11-22 23:47:08,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28241 states to 28241 states and 84261 transitions. [2018-11-22 23:47:08,691 INFO L78 Accepts]: Start accepts. Automaton has 28241 states and 84261 transitions. Word has length 68 [2018-11-22 23:47:08,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:08,691 INFO L480 AbstractCegarLoop]: Abstraction has 28241 states and 84261 transitions. [2018-11-22 23:47:08,691 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:08,691 INFO L276 IsEmpty]: Start isEmpty. Operand 28241 states and 84261 transitions. [2018-11-22 23:47:08,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:08,700 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:08,700 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:08,700 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:08,700 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:08,700 INFO L82 PathProgramCache]: Analyzing trace with hash 1298829570, now seen corresponding path program 1 times [2018-11-22 23:47:08,700 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:08,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:08,702 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:08,702 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:08,702 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:08,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:08,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:08,778 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:08,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:08,778 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:08,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:08,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:08,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:08,779 INFO L87 Difference]: Start difference. First operand 28241 states and 84261 transitions. Second operand 6 states. [2018-11-22 23:47:08,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:08,900 INFO L93 Difference]: Finished difference Result 28041 states and 79299 transitions. [2018-11-22 23:47:08,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 23:47:08,900 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2018-11-22 23:47:08,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:08,928 INFO L225 Difference]: With dead ends: 28041 [2018-11-22 23:47:08,928 INFO L226 Difference]: Without dead ends: 28041 [2018-11-22 23:47:08,928 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:08,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28041 states. [2018-11-22 23:47:09,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28041 to 23993. [2018-11-22 23:47:09,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23993 states. [2018-11-22 23:47:09,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23993 states to 23993 states and 68156 transitions. [2018-11-22 23:47:09,176 INFO L78 Accepts]: Start accepts. Automaton has 23993 states and 68156 transitions. Word has length 68 [2018-11-22 23:47:09,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:09,176 INFO L480 AbstractCegarLoop]: Abstraction has 23993 states and 68156 transitions. [2018-11-22 23:47:09,176 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:09,176 INFO L276 IsEmpty]: Start isEmpty. Operand 23993 states and 68156 transitions. [2018-11-22 23:47:09,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:09,185 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:09,185 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:09,185 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:09,186 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:09,186 INFO L82 PathProgramCache]: Analyzing trace with hash 389381892, now seen corresponding path program 1 times [2018-11-22 23:47:09,186 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:09,187 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,188 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:09,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,188 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:09,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:09,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:09,239 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:09,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:09,239 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:09,240 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:09,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:09,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:09,240 INFO L87 Difference]: Start difference. First operand 23993 states and 68156 transitions. Second operand 5 states. [2018-11-22 23:47:09,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:09,272 INFO L93 Difference]: Finished difference Result 7181 states and 17283 transitions. [2018-11-22 23:47:09,272 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 23:47:09,272 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2018-11-22 23:47:09,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:09,276 INFO L225 Difference]: With dead ends: 7181 [2018-11-22 23:47:09,276 INFO L226 Difference]: Without dead ends: 5896 [2018-11-22 23:47:09,277 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:09,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5896 states. [2018-11-22 23:47:09,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5896 to 5236. [2018-11-22 23:47:09,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5236 states. [2018-11-22 23:47:09,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5236 states to 5236 states and 12141 transitions. [2018-11-22 23:47:09,314 INFO L78 Accepts]: Start accepts. Automaton has 5236 states and 12141 transitions. Word has length 68 [2018-11-22 23:47:09,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:09,314 INFO L480 AbstractCegarLoop]: Abstraction has 5236 states and 12141 transitions. [2018-11-22 23:47:09,314 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:09,314 INFO L276 IsEmpty]: Start isEmpty. Operand 5236 states and 12141 transitions. [2018-11-22 23:47:09,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:47:09,318 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:09,318 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:09,318 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:09,318 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:09,319 INFO L82 PathProgramCache]: Analyzing trace with hash -342568837, now seen corresponding path program 1 times [2018-11-22 23:47:09,319 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:09,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:09,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,320 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:09,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:09,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:09,349 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:09,349 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:47:09,349 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:09,349 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:47:09,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:47:09,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:09,350 INFO L87 Difference]: Start difference. First operand 5236 states and 12141 transitions. Second operand 3 states. [2018-11-22 23:47:09,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:09,372 INFO L93 Difference]: Finished difference Result 6577 states and 15019 transitions. [2018-11-22 23:47:09,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:47:09,373 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2018-11-22 23:47:09,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:09,377 INFO L225 Difference]: With dead ends: 6577 [2018-11-22 23:47:09,377 INFO L226 Difference]: Without dead ends: 6577 [2018-11-22 23:47:09,377 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:47:09,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6577 states. [2018-11-22 23:47:09,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6577 to 5175. [2018-11-22 23:47:09,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5175 states. [2018-11-22 23:47:09,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5175 states to 5175 states and 11681 transitions. [2018-11-22 23:47:09,428 INFO L78 Accepts]: Start accepts. Automaton has 5175 states and 11681 transitions. Word has length 68 [2018-11-22 23:47:09,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:09,428 INFO L480 AbstractCegarLoop]: Abstraction has 5175 states and 11681 transitions. [2018-11-22 23:47:09,428 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:47:09,428 INFO L276 IsEmpty]: Start isEmpty. Operand 5175 states and 11681 transitions. [2018-11-22 23:47:09,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-22 23:47:09,433 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:09,433 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:09,433 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:09,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:09,434 INFO L82 PathProgramCache]: Analyzing trace with hash -571353426, now seen corresponding path program 1 times [2018-11-22 23:47:09,434 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:09,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:09,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,435 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:09,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:09,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:09,527 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:09,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:09,528 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:09,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:09,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:09,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:09,528 INFO L87 Difference]: Start difference. First operand 5175 states and 11681 transitions. Second operand 5 states. [2018-11-22 23:47:09,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:09,631 INFO L93 Difference]: Finished difference Result 6325 states and 14274 transitions. [2018-11-22 23:47:09,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-22 23:47:09,631 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 74 [2018-11-22 23:47:09,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:09,636 INFO L225 Difference]: With dead ends: 6325 [2018-11-22 23:47:09,636 INFO L226 Difference]: Without dead ends: 6325 [2018-11-22 23:47:09,636 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-11-22 23:47:09,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6325 states. [2018-11-22 23:47:09,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6325 to 5619. [2018-11-22 23:47:09,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5619 states. [2018-11-22 23:47:09,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5619 states to 5619 states and 12685 transitions. [2018-11-22 23:47:09,690 INFO L78 Accepts]: Start accepts. Automaton has 5619 states and 12685 transitions. Word has length 74 [2018-11-22 23:47:09,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:09,690 INFO L480 AbstractCegarLoop]: Abstraction has 5619 states and 12685 transitions. [2018-11-22 23:47:09,690 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:09,690 INFO L276 IsEmpty]: Start isEmpty. Operand 5619 states and 12685 transitions. [2018-11-22 23:47:09,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-22 23:47:09,694 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:09,694 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:09,694 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:09,694 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:09,694 INFO L82 PathProgramCache]: Analyzing trace with hash 1171456909, now seen corresponding path program 1 times [2018-11-22 23:47:09,695 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:09,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,696 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:09,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:09,696 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:09,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:09,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:09,758 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:09,758 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 23:47:09,758 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:09,758 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 23:47:09,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 23:47:09,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:09,759 INFO L87 Difference]: Start difference. First operand 5619 states and 12685 transitions. Second operand 7 states. [2018-11-22 23:47:09,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:09,968 INFO L93 Difference]: Finished difference Result 6586 states and 14710 transitions. [2018-11-22 23:47:09,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 23:47:09,968 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 74 [2018-11-22 23:47:09,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:09,972 INFO L225 Difference]: With dead ends: 6586 [2018-11-22 23:47:09,972 INFO L226 Difference]: Without dead ends: 6484 [2018-11-22 23:47:09,973 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=211, Unknown=0, NotChecked=0, Total=272 [2018-11-22 23:47:09,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6484 states. [2018-11-22 23:47:10,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6484 to 5716. [2018-11-22 23:47:10,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5716 states. [2018-11-22 23:47:10,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5716 states to 5716 states and 12778 transitions. [2018-11-22 23:47:10,013 INFO L78 Accepts]: Start accepts. Automaton has 5716 states and 12778 transitions. Word has length 74 [2018-11-22 23:47:10,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:10,014 INFO L480 AbstractCegarLoop]: Abstraction has 5716 states and 12778 transitions. [2018-11-22 23:47:10,014 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 23:47:10,014 INFO L276 IsEmpty]: Start isEmpty. Operand 5716 states and 12778 transitions. [2018-11-22 23:47:10,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 23:47:10,018 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:10,018 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:10,018 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:10,018 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:10,018 INFO L82 PathProgramCache]: Analyzing trace with hash 2144466605, now seen corresponding path program 1 times [2018-11-22 23:47:10,019 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:10,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,020 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:10,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,020 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:10,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:10,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:10,098 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:10,098 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 23:47:10,098 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:10,098 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 23:47:10,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 23:47:10,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:10,099 INFO L87 Difference]: Start difference. First operand 5716 states and 12778 transitions. Second operand 7 states. [2018-11-22 23:47:10,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:10,420 INFO L93 Difference]: Finished difference Result 7199 states and 16113 transitions. [2018-11-22 23:47:10,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:47:10,420 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 95 [2018-11-22 23:47:10,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:10,426 INFO L225 Difference]: With dead ends: 7199 [2018-11-22 23:47:10,426 INFO L226 Difference]: Without dead ends: 7199 [2018-11-22 23:47:10,426 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:10,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7199 states. [2018-11-22 23:47:10,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7199 to 5856. [2018-11-22 23:47:10,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5856 states. [2018-11-22 23:47:10,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5856 states to 5856 states and 13166 transitions. [2018-11-22 23:47:10,473 INFO L78 Accepts]: Start accepts. Automaton has 5856 states and 13166 transitions. Word has length 95 [2018-11-22 23:47:10,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:10,473 INFO L480 AbstractCegarLoop]: Abstraction has 5856 states and 13166 transitions. [2018-11-22 23:47:10,473 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 23:47:10,473 INFO L276 IsEmpty]: Start isEmpty. Operand 5856 states and 13166 transitions. [2018-11-22 23:47:10,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-11-22 23:47:10,477 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:10,478 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:10,478 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:10,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:10,478 INFO L82 PathProgramCache]: Analyzing trace with hash -1598659536, now seen corresponding path program 1 times [2018-11-22 23:47:10,478 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:10,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,479 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:10,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,479 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:10,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:10,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:10,536 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:10,536 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:10,536 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:10,537 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:10,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:10,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:10,537 INFO L87 Difference]: Start difference. First operand 5856 states and 13166 transitions. Second operand 4 states. [2018-11-22 23:47:10,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:10,597 INFO L93 Difference]: Finished difference Result 6980 states and 15568 transitions. [2018-11-22 23:47:10,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-22 23:47:10,598 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 95 [2018-11-22 23:47:10,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:10,603 INFO L225 Difference]: With dead ends: 6980 [2018-11-22 23:47:10,603 INFO L226 Difference]: Without dead ends: 6980 [2018-11-22 23:47:10,604 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:10,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6980 states. [2018-11-22 23:47:10,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6980 to 6213. [2018-11-22 23:47:10,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6213 states. [2018-11-22 23:47:10,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6213 states to 6213 states and 13936 transitions. [2018-11-22 23:47:10,651 INFO L78 Accepts]: Start accepts. Automaton has 6213 states and 13936 transitions. Word has length 95 [2018-11-22 23:47:10,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:10,651 INFO L480 AbstractCegarLoop]: Abstraction has 6213 states and 13936 transitions. [2018-11-22 23:47:10,652 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:10,652 INFO L276 IsEmpty]: Start isEmpty. Operand 6213 states and 13936 transitions. [2018-11-22 23:47:10,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:10,656 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:10,657 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:10,657 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:10,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:10,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1803412790, now seen corresponding path program 1 times [2018-11-22 23:47:10,657 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:10,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:10,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,658 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:10,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:10,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:10,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:10,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:10,709 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:10,709 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:10,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:10,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:10,710 INFO L87 Difference]: Start difference. First operand 6213 states and 13936 transitions. Second operand 5 states. [2018-11-22 23:47:10,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:10,813 INFO L93 Difference]: Finished difference Result 6659 states and 14882 transitions. [2018-11-22 23:47:10,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:47:10,814 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 97 [2018-11-22 23:47:10,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:10,818 INFO L225 Difference]: With dead ends: 6659 [2018-11-22 23:47:10,818 INFO L226 Difference]: Without dead ends: 6659 [2018-11-22 23:47:10,818 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:10,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6659 states. [2018-11-22 23:47:10,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6659 to 5109. [2018-11-22 23:47:10,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5109 states. [2018-11-22 23:47:10,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5109 states to 5109 states and 11452 transitions. [2018-11-22 23:47:10,856 INFO L78 Accepts]: Start accepts. Automaton has 5109 states and 11452 transitions. Word has length 97 [2018-11-22 23:47:10,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:10,856 INFO L480 AbstractCegarLoop]: Abstraction has 5109 states and 11452 transitions. [2018-11-22 23:47:10,856 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:10,856 INFO L276 IsEmpty]: Start isEmpty. Operand 5109 states and 11452 transitions. [2018-11-22 23:47:10,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:10,860 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:10,860 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:10,860 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:10,860 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:10,860 INFO L82 PathProgramCache]: Analyzing trace with hash 1814728917, now seen corresponding path program 1 times [2018-11-22 23:47:10,860 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:10,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:10,862 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:10,862 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:10,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:10,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:10,930 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:10,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-22 23:47:10,931 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:10,931 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-22 23:47:10,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-22 23:47:10,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-22 23:47:10,931 INFO L87 Difference]: Start difference. First operand 5109 states and 11452 transitions. Second operand 4 states. [2018-11-22 23:47:11,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:11,047 INFO L93 Difference]: Finished difference Result 6613 states and 14743 transitions. [2018-11-22 23:47:11,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-22 23:47:11,048 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 97 [2018-11-22 23:47:11,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:11,052 INFO L225 Difference]: With dead ends: 6613 [2018-11-22 23:47:11,052 INFO L226 Difference]: Without dead ends: 6566 [2018-11-22 23:47:11,052 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:11,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6566 states. [2018-11-22 23:47:11,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6566 to 6157. [2018-11-22 23:47:11,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6157 states. [2018-11-22 23:47:11,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6157 states to 6157 states and 13768 transitions. [2018-11-22 23:47:11,095 INFO L78 Accepts]: Start accepts. Automaton has 6157 states and 13768 transitions. Word has length 97 [2018-11-22 23:47:11,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:11,095 INFO L480 AbstractCegarLoop]: Abstraction has 6157 states and 13768 transitions. [2018-11-22 23:47:11,095 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-22 23:47:11,095 INFO L276 IsEmpty]: Start isEmpty. Operand 6157 states and 13768 transitions. [2018-11-22 23:47:11,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:11,099 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:11,099 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:11,099 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:11,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:11,099 INFO L82 PathProgramCache]: Analyzing trace with hash -262480426, now seen corresponding path program 1 times [2018-11-22 23:47:11,100 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:11,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:11,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:11,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:11,101 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:11,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:11,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:11,220 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:11,220 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-11-22 23:47:11,220 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:11,220 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-22 23:47:11,220 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-22 23:47:11,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-11-22 23:47:11,221 INFO L87 Difference]: Start difference. First operand 6157 states and 13768 transitions. Second operand 9 states. [2018-11-22 23:47:11,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:11,609 INFO L93 Difference]: Finished difference Result 7878 states and 17405 transitions. [2018-11-22 23:47:11,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-11-22 23:47:11,610 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 97 [2018-11-22 23:47:11,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:11,618 INFO L225 Difference]: With dead ends: 7878 [2018-11-22 23:47:11,618 INFO L226 Difference]: Without dead ends: 7878 [2018-11-22 23:47:11,618 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=320, Unknown=0, NotChecked=0, Total=420 [2018-11-22 23:47:11,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7878 states. [2018-11-22 23:47:11,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7878 to 6683. [2018-11-22 23:47:11,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6683 states. [2018-11-22 23:47:11,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6683 states to 6683 states and 14838 transitions. [2018-11-22 23:47:11,694 INFO L78 Accepts]: Start accepts. Automaton has 6683 states and 14838 transitions. Word has length 97 [2018-11-22 23:47:11,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:11,695 INFO L480 AbstractCegarLoop]: Abstraction has 6683 states and 14838 transitions. [2018-11-22 23:47:11,695 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-22 23:47:11,695 INFO L276 IsEmpty]: Start isEmpty. Operand 6683 states and 14838 transitions. [2018-11-22 23:47:11,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:11,701 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:11,701 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:11,701 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:11,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:11,702 INFO L82 PathProgramCache]: Analyzing trace with hash -51129513, now seen corresponding path program 1 times [2018-11-22 23:47:11,702 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:11,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:11,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:11,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:11,703 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:11,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:11,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:11,889 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:11,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-11-22 23:47:11,889 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:11,889 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 23:47:11,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 23:47:11,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-22 23:47:11,889 INFO L87 Difference]: Start difference. First operand 6683 states and 14838 transitions. Second operand 11 states. [2018-11-22 23:47:13,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:13,208 INFO L93 Difference]: Finished difference Result 12276 states and 27352 transitions. [2018-11-22 23:47:13,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-22 23:47:13,209 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 97 [2018-11-22 23:47:13,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:13,215 INFO L225 Difference]: With dead ends: 12276 [2018-11-22 23:47:13,215 INFO L226 Difference]: Without dead ends: 8479 [2018-11-22 23:47:13,215 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=86, Invalid=376, Unknown=0, NotChecked=0, Total=462 [2018-11-22 23:47:13,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8479 states. [2018-11-22 23:47:13,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8479 to 6439. [2018-11-22 23:47:13,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6439 states. [2018-11-22 23:47:13,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6439 states to 6439 states and 14285 transitions. [2018-11-22 23:47:13,269 INFO L78 Accepts]: Start accepts. Automaton has 6439 states and 14285 transitions. Word has length 97 [2018-11-22 23:47:13,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:13,270 INFO L480 AbstractCegarLoop]: Abstraction has 6439 states and 14285 transitions. [2018-11-22 23:47:13,270 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 23:47:13,270 INFO L276 IsEmpty]: Start isEmpty. Operand 6439 states and 14285 transitions. [2018-11-22 23:47:13,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:13,275 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:13,275 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:13,275 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:13,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:13,275 INFO L82 PathProgramCache]: Analyzing trace with hash 746604445, now seen corresponding path program 1 times [2018-11-22 23:47:13,275 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:13,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:13,277 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:13,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:13,277 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:13,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:13,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:13,471 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:13,471 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:13,471 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:13,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:13,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:13,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:13,472 INFO L87 Difference]: Start difference. First operand 6439 states and 14285 transitions. Second operand 6 states. [2018-11-22 23:47:13,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:13,726 INFO L93 Difference]: Finished difference Result 7393 states and 16150 transitions. [2018-11-22 23:47:13,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:47:13,727 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 97 [2018-11-22 23:47:13,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:13,734 INFO L225 Difference]: With dead ends: 7393 [2018-11-22 23:47:13,734 INFO L226 Difference]: Without dead ends: 7362 [2018-11-22 23:47:13,734 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:13,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7362 states. [2018-11-22 23:47:13,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7362 to 6492. [2018-11-22 23:47:13,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6492 states. [2018-11-22 23:47:13,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6492 states to 6492 states and 14216 transitions. [2018-11-22 23:47:13,810 INFO L78 Accepts]: Start accepts. Automaton has 6492 states and 14216 transitions. Word has length 97 [2018-11-22 23:47:13,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:13,811 INFO L480 AbstractCegarLoop]: Abstraction has 6492 states and 14216 transitions. [2018-11-22 23:47:13,811 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:13,811 INFO L276 IsEmpty]: Start isEmpty. Operand 6492 states and 14216 transitions. [2018-11-22 23:47:13,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:13,817 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:13,818 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:13,818 INFO L423 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:13,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:13,818 INFO L82 PathProgramCache]: Analyzing trace with hash 993123225, now seen corresponding path program 1 times [2018-11-22 23:47:13,818 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:13,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:13,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:13,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:13,820 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:13,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:13,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:13,866 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:13,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:47:13,866 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:13,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:47:13,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:47:13,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:47:13,867 INFO L87 Difference]: Start difference. First operand 6492 states and 14216 transitions. Second operand 5 states. [2018-11-22 23:47:14,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:14,032 INFO L93 Difference]: Finished difference Result 7692 states and 16739 transitions. [2018-11-22 23:47:14,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 23:47:14,033 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 97 [2018-11-22 23:47:14,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:14,037 INFO L225 Difference]: With dead ends: 7692 [2018-11-22 23:47:14,037 INFO L226 Difference]: Without dead ends: 7605 [2018-11-22 23:47:14,038 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:47:14,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7605 states. [2018-11-22 23:47:14,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7605 to 6147. [2018-11-22 23:47:14,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6147 states. [2018-11-22 23:47:14,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6147 states to 6147 states and 13534 transitions. [2018-11-22 23:47:14,087 INFO L78 Accepts]: Start accepts. Automaton has 6147 states and 13534 transitions. Word has length 97 [2018-11-22 23:47:14,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:14,087 INFO L480 AbstractCegarLoop]: Abstraction has 6147 states and 13534 transitions. [2018-11-22 23:47:14,087 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:47:14,087 INFO L276 IsEmpty]: Start isEmpty. Operand 6147 states and 13534 transitions. [2018-11-22 23:47:14,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:14,091 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:14,091 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:14,091 INFO L423 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:14,091 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:14,091 INFO L82 PathProgramCache]: Analyzing trace with hash 1717244729, now seen corresponding path program 2 times [2018-11-22 23:47:14,092 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:14,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:14,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,093 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:14,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:14,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:14,168 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:14,168 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-22 23:47:14,168 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:14,168 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-22 23:47:14,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-22 23:47:14,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-22 23:47:14,169 INFO L87 Difference]: Start difference. First operand 6147 states and 13534 transitions. Second operand 7 states. [2018-11-22 23:47:14,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:14,438 INFO L93 Difference]: Finished difference Result 8233 states and 17820 transitions. [2018-11-22 23:47:14,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-22 23:47:14,438 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 97 [2018-11-22 23:47:14,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:14,444 INFO L225 Difference]: With dead ends: 8233 [2018-11-22 23:47:14,444 INFO L226 Difference]: Without dead ends: 8233 [2018-11-22 23:47:14,444 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=125, Unknown=0, NotChecked=0, Total=182 [2018-11-22 23:47:14,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8233 states. [2018-11-22 23:47:14,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8233 to 6657. [2018-11-22 23:47:14,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6657 states. [2018-11-22 23:47:14,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6657 states to 6657 states and 14640 transitions. [2018-11-22 23:47:14,494 INFO L78 Accepts]: Start accepts. Automaton has 6657 states and 14640 transitions. Word has length 97 [2018-11-22 23:47:14,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:14,495 INFO L480 AbstractCegarLoop]: Abstraction has 6657 states and 14640 transitions. [2018-11-22 23:47:14,495 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-22 23:47:14,495 INFO L276 IsEmpty]: Start isEmpty. Operand 6657 states and 14640 transitions. [2018-11-22 23:47:14,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:14,499 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:14,499 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:14,499 INFO L423 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:14,499 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:14,499 INFO L82 PathProgramCache]: Analyzing trace with hash 1928595642, now seen corresponding path program 1 times [2018-11-22 23:47:14,499 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:14,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,501 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 23:47:14,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,501 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:14,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:14,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:14,557 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:14,557 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-22 23:47:14,557 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:14,558 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-22 23:47:14,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-22 23:47:14,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-22 23:47:14,558 INFO L87 Difference]: Start difference. First operand 6657 states and 14640 transitions. Second operand 6 states. [2018-11-22 23:47:14,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:14,665 INFO L93 Difference]: Finished difference Result 7077 states and 15492 transitions. [2018-11-22 23:47:14,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-22 23:47:14,666 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 97 [2018-11-22 23:47:14,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:14,671 INFO L225 Difference]: With dead ends: 7077 [2018-11-22 23:47:14,671 INFO L226 Difference]: Without dead ends: 7077 [2018-11-22 23:47:14,671 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:47:14,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7077 states. [2018-11-22 23:47:14,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7077 to 6577. [2018-11-22 23:47:14,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6577 states. [2018-11-22 23:47:14,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6577 states to 6577 states and 14450 transitions. [2018-11-22 23:47:14,718 INFO L78 Accepts]: Start accepts. Automaton has 6577 states and 14450 transitions. Word has length 97 [2018-11-22 23:47:14,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:14,719 INFO L480 AbstractCegarLoop]: Abstraction has 6577 states and 14450 transitions. [2018-11-22 23:47:14,719 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-22 23:47:14,719 INFO L276 IsEmpty]: Start isEmpty. Operand 6577 states and 14450 transitions. [2018-11-22 23:47:14,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:14,723 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:14,723 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:14,723 INFO L423 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:14,723 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:14,724 INFO L82 PathProgramCache]: Analyzing trace with hash -1915558852, now seen corresponding path program 2 times [2018-11-22 23:47:14,724 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:14,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,725 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:47:14,725 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:14,725 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:14,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:47:14,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:47:14,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:47:14,811 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-22 23:47:14,811 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-22 23:47:14,812 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-22 23:47:14,812 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-22 23:47:14,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:47:14,812 INFO L87 Difference]: Start difference. First operand 6577 states and 14450 transitions. Second operand 8 states. [2018-11-22 23:47:15,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:47:15,047 INFO L93 Difference]: Finished difference Result 8103 states and 17596 transitions. [2018-11-22 23:47:15,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-22 23:47:15,048 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 97 [2018-11-22 23:47:15,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:47:15,053 INFO L225 Difference]: With dead ends: 8103 [2018-11-22 23:47:15,053 INFO L226 Difference]: Without dead ends: 8103 [2018-11-22 23:47:15,054 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 5 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-11-22 23:47:15,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8103 states. [2018-11-22 23:47:15,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8103 to 6615. [2018-11-22 23:47:15,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6615 states. [2018-11-22 23:47:15,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6615 states to 6615 states and 14550 transitions. [2018-11-22 23:47:15,108 INFO L78 Accepts]: Start accepts. Automaton has 6615 states and 14550 transitions. Word has length 97 [2018-11-22 23:47:15,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:47:15,108 INFO L480 AbstractCegarLoop]: Abstraction has 6615 states and 14550 transitions. [2018-11-22 23:47:15,108 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-22 23:47:15,108 INFO L276 IsEmpty]: Start isEmpty. Operand 6615 states and 14550 transitions. [2018-11-22 23:47:15,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-22 23:47:15,113 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:47:15,113 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:47:15,113 INFO L423 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:47:15,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:47:15,113 INFO L82 PathProgramCache]: Analyzing trace with hash -1704207939, now seen corresponding path program 2 times [2018-11-22 23:47:15,113 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-22 23:47:15,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:15,115 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-22 23:47:15,115 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:47:15,115 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-22 23:47:15,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 23:47:15,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 23:47:15,165 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [477] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [362] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [523] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [388] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [426] L675-->L677: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [484] L677-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [421] L678-->L679: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [530] L679-->L681: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [393] L681-->L683: Formula: (= v_~x~0_3 0) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [454] L683-->L685: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [490] L685-->L686: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [423] L686-->L687: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [380] L687-->L688: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [483] L688-->L689: Formula: (= v_~z$r_buff0_thd0~0_2 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [420] L689-->L690: Formula: (= v_~z$r_buff0_thd1~0_14 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [529] L690-->L691: Formula: (= v_~z$r_buff0_thd2~0_43 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [465] L691-->L692: Formula: (= v_~z$r_buff1_thd0~0_2 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~z$r_buff1_thd1~0_9 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [521] L693-->L694: Formula: (= v_~z$r_buff1_thd2~0_25 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [453] L694-->L695: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [387] L695-->L696: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [489] L696-->L697: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [422] L697-->L698: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [377] L698-->L699: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [482] L699-->L700: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L700-->L701: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [528] L701-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [522] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [515] L-1-2-->L780: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_1|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_1|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t908~0.offset, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_~#t907~0.offset, ULTIMATE.start_main_~#t908~0.base, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t907~0.base, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [410] L780-->L780-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t907~0.base_2| 1) |v_#valid_1|) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t907~0.base_2| 4)) (= 0 (select |v_#valid_2| |v_ULTIMATE.start_main_~#t907~0.base_2|)) (not (= 0 |v_ULTIMATE.start_main_~#t907~0.base_2|)) (= 0 |v_ULTIMATE.start_main_~#t907~0.offset_2|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_2|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_2|, #length=|v_#length_1|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t907~0.offset, #valid, ULTIMATE.start_main_~#t907~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [414] L780-1-->L781: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t907~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t907~0.base_3|) |v_ULTIMATE.start_main_~#t907~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_3|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_3|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [646] L781-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [514] L781-1-->L782: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [534] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~z$w_buff0~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_1 256))) (not (= (mod v_~z$w_buff0_used~0_1 256) 0)))) 1 0)) (= v_~z$w_buff1_used~0_1 v_~z$w_buff0_used~0_2) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_1 1) (= v_~z$w_buff1~0_1 v_~z$w_buff0~0_2)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_2, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1, ~z$w_buff0~0=v_~z$w_buff0~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_1, ~z$w_buff1~0=v_~z$w_buff1~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [536] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [539] L4-3-->L719: Formula: (and (= v_~z$r_buff1_thd2~0_1 v_~z$r_buff0_thd2~0_1) (= v_~__unbuffered_p0_EAX~0_1 v_~x~0_1) (= v_~z$r_buff0_thd1~0_1 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_2)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2, ~x~0=v_~x~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_1} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~x~0=v_~x~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [540] L719-->L719-5: Formula: (and (= |v_Thread0_P0_#t~ite4_1| v_~z$w_buff0~0_3) (not (= (mod v_~z$w_buff0_used~0_3 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd1~0_3 256)))) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [447] L782-->L782-1: Formula: (and (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t908~0.base_2|) 0) (= 0 |v_ULTIMATE.start_main_~#t908~0.offset_2|) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t908~0.base_2| 1)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t908~0.base_2| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t908~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_2|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_2|, #length=|v_#length_3|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t908~0.offset, ULTIMATE.start_main_~#t908~0.base, #valid, #length] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [448] L782-1-->L783: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t908~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t908~0.base_3|) |v_ULTIMATE.start_main_~#t908~0.offset_3| 1))) InVars {ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_3|, #memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_3|} OutVars{ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_3|, #memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [647] L783-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [561] P1ENTRY-->L746: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_3) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~x~0_2 1) (= v_~y~0_1 1) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, ~z~0=v_~z~0_3, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~z~0=v_~z~0_3, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_1, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, ~z$flush_delayed~0, Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, Thread1_P1_#t~nondet11.base, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [562] L746-->L746-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_15 256) 0))) (or (= 0 (mod v_~z$w_buff0_used~0_26 256)) (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_9 256))) (and .cse0 (= (mod v_~z$w_buff1_used~0_17 256) 0)))) (= |v_Thread1_P1_#t~ite13_1| v_~z~0_4)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z~0=v_~z~0_4, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_26, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_15, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_9} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_26, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_9, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~z~0=v_~z~0_4, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [564] L746-5-->L747: Formula: (= v_~z~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [567] L747-->L747-8: Formula: (and (= |v_Thread1_P1_#t~ite16_1| v_~z$w_buff0~0_5) (not (= (mod v_~weak$$choice2~0_8 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~z$w_buff0~0=v_~z$w_buff0~0_5} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|, ~z$w_buff0~0=v_~z$w_buff0~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [570] L747-8-->L748: Formula: (= v_~z$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, ~z$w_buff0~0=v_~z$w_buff0~0_10, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [573] L748-->L748-8: Formula: (and (= |v_Thread1_P1_#t~ite19_1| v_~z$w_buff1~0_5) (not (= (mod v_~weak$$choice2~0_10 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~z$w_buff1~0=v_~z$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~z$w_buff1~0=v_~z$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [578] L748-8-->L749: Formula: (= v_~z$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, ~z$w_buff1~0=v_~z$w_buff1~0_9, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~z$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [582] L749-->L749-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~z$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [587] L749-8-->L750: Formula: (= v_~z$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_15, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [591] L750-->L750-8: Formula: (and (not (= (mod v_~weak$$choice2~0_1 256) 0)) (= |v_Thread1_P1_#t~ite25_1| v_~z$w_buff1_used~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [596] L750-8-->L751: Formula: (= v_~z$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~z$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [600] L751-->L751-8: Formula: (and (= |v_Thread1_P1_#t~ite28_1| v_~z$r_buff0_thd2~0_7) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [605] L751-8-->L752: Formula: (= v_~z$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_12, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, Thread1_P1_#t~ite26, ~z$r_buff0_thd2~0, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [609] L752-->L752-8: Formula: (and (= |v_Thread1_P1_#t~ite31_1| v_~z$r_buff1_thd2~0_6) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_6} OutVars{Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [614] L752-8-->L754: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_5) (= v_~z$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~z~0=v_~z~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_11, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~z~0=v_~z~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, ~z$r_buff1_thd2~0, Thread1_P1_#t~ite30, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [618] L754-->L754-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread1_P1_#t~ite32_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [542] L719-5-->L720: Formula: (= v_~z~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~z~0=v_~z~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [545] L720-->L720-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~z$r_buff0_thd1~0_5 256))) (not (= (mod v_~z$w_buff0_used~0_5 256) 0))) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [548] L720-2-->L721: Formula: (= v_~z$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_7} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [550] L721-->L721-2: Formula: (and (or (= (mod v_~z$w_buff1_used~0_5 256) 0) (= 0 (mod v_~z$r_buff1_thd1~0_5 256))) (= |v_Thread0_P0_#t~ite6_2| v_~z$w_buff1_used~0_5) (or (= 0 (mod v_~z$w_buff0_used~0_9 256)) (= (mod v_~z$r_buff0_thd1~0_8 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_5, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_9, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_5, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_9, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [551] L721-2-->L722: Formula: (= v_~z$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [553] L722-->L722-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_11 256) 0) (= 0 (mod v_~z$r_buff0_thd1~0_10 256))) (= |v_Thread0_P0_#t~ite7_2| v_~z$r_buff0_thd1~0_10)) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [554] L722-2-->L723: Formula: (= v_~z$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_11, Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite7, ~z$r_buff0_thd1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [556] L723-->L723-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd1~0_13 256)) (= (mod v_~z$w_buff0_used~0_13 256) 0)) (or (= (mod v_~z$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~z$w_buff1_used~0_8 256))) (= |v_Thread0_P0_#t~ite8_2| v_~z$r_buff1_thd1~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_13, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_13, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [557] L723-2-->L728: Formula: (and (= v_~z$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_8} AuxVars[] AssignedVars[~z$r_buff1_thd1~0, ~__unbuffered_cnt~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 [623] L754-2-->L758: Formula: (and (= v_~z~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~z$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_8, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [626] L758-->L758-2: Formula: (or (= 0 (mod v_~z$r_buff0_thd2~0_24 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_24} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_24} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [629] L758-2-->L758-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~z~0_9) (or (= 0 (mod v_~z$r_buff1_thd2~0_15 256)) (= 0 (mod v_~z$w_buff1_used~0_22 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_22, ~z~0=v_~z~0_9, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_15} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_22, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~z~0=v_~z~0_9, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [632] L758-4-->L758-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [627] L758-5-->L759: Formula: (= v_~z~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~z~0=v_~z~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [631] L759-->L759-2: Formula: (and (= |v_Thread1_P1_#t~ite35_2| v_~z$w_buff0_used~0_39) (or (= 0 (mod v_~z$r_buff0_thd2~0_28 256)) (= 0 (mod v_~z$w_buff0_used~0_39 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_39, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_28} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_39, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_28} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [633] L759-2-->L760: Formula: (= v_~z$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [635] L760-->L760-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~z$w_buff1_used~0_26) (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd2~0_19 256) 0)) (or (= (mod v_~z$r_buff0_thd2~0_32 256) 0) (= 0 (mod v_~z$w_buff0_used~0_44 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_44, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_19} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_44, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_19} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [636] L760-2-->L761: Formula: (= v_~z$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [638] L761-->L761-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd2~0_36 256)) (= 0 (mod v_~z$w_buff0_used~0_48 256))) (= |v_Thread1_P1_#t~ite37_2| v_~z$r_buff0_thd2~0_36)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_36} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [639] L761-2-->L762: Formula: (= v_~z$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~z$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [641] L762-->L762-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_51 256) 0) (= (mod v_~z$r_buff0_thd2~0_39 256) 0)) (or (= (mod v_~z$w_buff1_used~0_29 256) 0) (= (mod v_~z$r_buff1_thd2~0_21 256) 0)) (= |v_Thread1_P1_#t~ite38_2| v_~z$r_buff1_thd2~0_21)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_51, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_39, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_51, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_39, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [642] L762-2-->L767: Formula: (and (= v_~z$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_22, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [384] L783-1-->L787: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [478] L787-->L789: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [361] L789-->L789-2: Formula: (or (= (mod v_~z$w_buff0_used~0_57 256) 0) (= (mod v_~z$r_buff0_thd0~0_4 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_57, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_4} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_57, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_4} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [527] L789-2-->L789-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~z~0_12) (or (= (mod v_~z$r_buff1_thd0~0_4 256) 0) (= 0 (mod v_~z$w_buff1_used~0_34 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_34, ~z~0=v_~z~0_12, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_4} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_34, ~z~0=v_~z~0_12, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_4} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [531] L789-4-->L789-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [532] L789-5-->L790: Formula: (= v_~z~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{~z~0=v_~z~0_13, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|} AuxVars[] AssignedVars[~z~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [471] L790-->L790-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_59 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_6 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~z$w_buff0_used~0_59)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_6} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L790-2-->L791: Formula: (= v_~z$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_60, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [409] L791-->L791-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite45_3| v_~z$w_buff1_used~0_36) (or (= (mod v_~z$w_buff0_used~0_62 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_8 256))) (or (= (mod v_~z$w_buff1_used~0_36 256) 0) (= 0 (mod v_~z$r_buff1_thd0~0_6 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_36, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_62, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_6} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_36, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_62, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [415] L791-2-->L792: Formula: (= v_~z$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [510] L792-->L792-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_64 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_10 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~z$r_buff0_thd0~0_10)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_64, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [516] L792-2-->L793: Formula: (= v_~z$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_11} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [446] L793-->L793-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~z$r_buff1_thd0~0_8) (or (= 0 (mod v_~z$r_buff1_thd0~0_8 256)) (= (mod v_~z$w_buff1_used~0_39 256) 0)) (or (= 0 (mod v_~z$r_buff0_thd0~0_13 256)) (= (mod v_~z$w_buff0_used~0_66 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_39, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_39, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [451] L793-2-->L798: Formula: (and (= v_~z$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EAX~0_2 0))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [476] L798-->L798-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L798-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [404] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); srcloc: L780-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff0_thd1~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite4 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); srcloc: L782 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); srcloc: L782-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 1;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite13 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite14;havoc #t~ite15; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1~0 := #t~ite19;havoc #t~ite17;havoc #t~ite19;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite22;havoc #t~ite20; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite28;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite31;havoc #t~ite29;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~z$flush_delayed~0 % 256;#t~ite32 := ~z$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite6 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256);#t~ite7 := ~z$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite8 := ~z$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 ~z~0 := #t~ite32;havoc #t~ite32;~z$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256);#t~ite33 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite34;havoc #t~ite33;havoc #t~ite34; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite35 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite36 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite37 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite38 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite42 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite44 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite45 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); srcloc: L780-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff0_thd1~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite4 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); srcloc: L782 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); srcloc: L782-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 1;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite13 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite14;havoc #t~ite15; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1~0 := #t~ite19;havoc #t~ite17;havoc #t~ite19;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite22;havoc #t~ite20; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite28;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite31;havoc #t~ite29;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~z$flush_delayed~0 % 256;#t~ite32 := ~z$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite6 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256);#t~ite7 := ~z$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite8 := ~z$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 ~z~0 := #t~ite32;havoc #t~ite32;~z$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256);#t~ite33 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite34;havoc #t~ite33;havoc #t~ite34; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite35 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite36 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite37 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite38 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite42 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite44 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite45 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] -1 call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] -1 call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L742] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L743] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 assume 0 != ~weak$$choice2~0 % 256; [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 assume 0 != ~weak$$choice2~0 % 256; [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] 1 assume 0 != ~z$flush_delayed~0 % 256; [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L720] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256); [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256); [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] -1 call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] -1 call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L742] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L743] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 assume 0 != ~weak$$choice2~0 % 256; [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 assume 0 != ~weak$$choice2~0 % 256; [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] 1 assume 0 != ~z$flush_delayed~0 % 256; [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L720] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256); [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256); [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0, main_~#t908~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call main_~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, main_~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call main_~#t908~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, main_~#t908~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0, main_~#t908~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call main_~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, main_~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call main_~#t908~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, main_~#t908~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call ~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, ~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call ~#t908~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, ~#t908~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc #t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 #t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := #t~ite43; [L789] -1 havoc #t~ite42; [L789] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 #t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := #t~ite44; [L790] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := #t~ite45; [L791] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 #t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := #t~ite46; [L792] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 #t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := #t~ite47; [L793] -1 havoc #t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call ~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, ~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call ~#t908~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, ~#t908~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc #t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 #t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := #t~ite43; [L789] -1 havoc #t~ite42; [L789] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 #t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := #t~ite44; [L790] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := #t~ite45; [L791] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 #t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := #t~ite46; [L792] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 #t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := #t~ite47; [L793] -1 havoc #t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L677] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L679] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L681] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L683] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L685] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L686] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L687] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L688] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L689] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L690] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L691] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0] [L692] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L693] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L694] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0] [L695] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L696] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L697] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L698] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L699] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L700] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L701] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L780] -1 pthread_t t907; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L781] FCALL, FORK -1 pthread_create(&t907, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L705] 0 z$w_buff1 = z$w_buff0 [L706] 0 z$w_buff0 = 1 [L707] 0 z$w_buff1_used = z$w_buff0_used [L708] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L710] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L711] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L712] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L713] 0 z$r_buff0_thd1 = (_Bool)1 [L716] 0 __unbuffered_p0_EAX = x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L782] -1 pthread_t t908; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L783] FCALL, FORK -1 pthread_create(&t908, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L733] 1 x = 1 [L736] 1 y = 1 [L739] 1 __unbuffered_p1_EAX = y [L742] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L743] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L744] 1 z$flush_delayed = weak$$choice2 [L745] 1 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] EXPR 1 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] 1 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L747] EXPR 1 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L747] 1 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L748] EXPR 1 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L748] 1 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L749] EXPR 1 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L749] 1 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L750] EXPR 1 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] 1 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] EXPR 1 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L751] 1 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L752] EXPR 1 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L752] 1 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L753] 1 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L754] EXPR 1 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] 0 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L720] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L720] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L721] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L721] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L722] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L722] 0 z$r_buff0_thd1 = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 [L723] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L723] 0 z$r_buff1_thd1 = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 [L726] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L754] 1 z = z$flush_delayed ? z$mem_tmp : z [L755] 1 z$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] 1 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L759] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L759] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L760] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L760] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L761] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L761] 1 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L762] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L762] 1 z$r_buff1_thd2 = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 [L765] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L785] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L790] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L790] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L791] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L791] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L792] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L792] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L793] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L793] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L796] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-22 23:47:17,097 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-22 23:47:17,098 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.11 11:47:17 BasicIcfg [2018-11-22 23:47:17,098 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-22 23:47:17,099 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 23:47:17,099 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 23:47:17,099 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 23:47:17,099 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:46:58" (3/4) ... [2018-11-22 23:47:17,101 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [477] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [362] L-1-->L671: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [523] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_6 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [388] L673-->L675: Formula: (= v_~__unbuffered_p0_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 [426] L675-->L677: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [484] L677-->L678: Formula: (= v_~__unbuffered_p1_EBX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 [421] L678-->L679: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 [530] L679-->L681: Formula: (= v_~main$tmp_guard1~0_1 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_1} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [393] L681-->L683: Formula: (= v_~x~0_3 0) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [454] L683-->L685: Formula: (= v_~y~0_2 0) InVars {} OutVars{~y~0=v_~y~0_2} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 [490] L685-->L686: Formula: (= v_~z~0_11 0) InVars {} OutVars{~z~0=v_~z~0_11} AuxVars[] AssignedVars[~z~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 [423] L686-->L687: Formula: (= v_~z$flush_delayed~0_5 0) InVars {} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_5} AuxVars[] AssignedVars[~z$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 [380] L687-->L688: Formula: (= v_~z$mem_tmp~0_3 0) InVars {} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_3} AuxVars[] AssignedVars[~z$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 [483] L688-->L689: Formula: (= v_~z$r_buff0_thd0~0_2 0) InVars {} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_2} AuxVars[] AssignedVars[~z$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 [420] L689-->L690: Formula: (= v_~z$r_buff0_thd1~0_14 0) InVars {} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_14} AuxVars[] AssignedVars[~z$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 [529] L690-->L691: Formula: (= v_~z$r_buff0_thd2~0_43 0) InVars {} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_43} AuxVars[] AssignedVars[~z$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 [465] L691-->L692: Formula: (= v_~z$r_buff1_thd0~0_2 0) InVars {} OutVars{~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 [392] L692-->L693: Formula: (= v_~z$r_buff1_thd1~0_9 0) InVars {} OutVars{~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~z$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 [521] L693-->L694: Formula: (= v_~z$r_buff1_thd2~0_25 0) InVars {} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_25} AuxVars[] AssignedVars[~z$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 [453] L694-->L695: Formula: (= v_~z$read_delayed~0_1 0) InVars {} OutVars{~z$read_delayed~0=v_~z$read_delayed~0_1} AuxVars[] AssignedVars[~z$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [387] L695-->L696: Formula: (and (= v_~z$read_delayed_var~0.offset_1 0) (= v_~z$read_delayed_var~0.base_1 0)) InVars {} OutVars{~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_1, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 [489] L696-->L697: Formula: (= v_~z$w_buff0~0_11 0) InVars {} OutVars{~z$w_buff0~0=v_~z$w_buff0~0_11} AuxVars[] AssignedVars[~z$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [422] L697-->L698: Formula: (= v_~z$w_buff0_used~0_55 0) InVars {} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_55} AuxVars[] AssignedVars[~z$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 [377] L698-->L699: Formula: (= v_~z$w_buff1~0_10 0) InVars {} OutVars{~z$w_buff1~0=v_~z$w_buff1~0_10} AuxVars[] AssignedVars[~z$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [482] L699-->L700: Formula: (= v_~z$w_buff1_used~0_32 0) InVars {} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_32} AuxVars[] AssignedVars[~z$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [419] L700-->L701: Formula: (= v_~weak$$choice0~0_2 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [528] L701-->L-1-1: Formula: (= v_~weak$$choice2~0_14 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_14} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [522] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [515] L-1-2-->L780: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_1|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_1|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_1|, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_1|, ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_1|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t908~0.offset, ULTIMATE.start_main_#t~nondet40, ULTIMATE.start_main_~#t907~0.offset, ULTIMATE.start_main_~#t908~0.base, ULTIMATE.start_main_#t~nondet41, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t907~0.base, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [410] L780-->L780-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t907~0.base_2| 1) |v_#valid_1|) (= |v_#length_1| (store |v_#length_2| |v_ULTIMATE.start_main_~#t907~0.base_2| 4)) (= 0 (select |v_#valid_2| |v_ULTIMATE.start_main_~#t907~0.base_2|)) (not (= 0 |v_ULTIMATE.start_main_~#t907~0.base_2|)) (= 0 |v_ULTIMATE.start_main_~#t907~0.offset_2|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_2|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_2|, #length=|v_#length_1|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t907~0.offset, #valid, ULTIMATE.start_main_~#t907~0.base, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [414] L780-1-->L781: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t907~0.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t907~0.base_3|) |v_ULTIMATE.start_main_~#t907~0.offset_3| 0))) InVars {#memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_3|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_3|} OutVars{#memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t907~0.base=|v_ULTIMATE.start_main_~#t907~0.base_3|, ULTIMATE.start_main_~#t907~0.offset=|v_ULTIMATE.start_main_~#t907~0.offset_3|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [646] L781-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [514] L781-1-->L782: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet40=|v_ULTIMATE.start_main_#t~nondet40_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet40] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [534] P0ENTRY-->L4: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~z$w_buff0~0_1 1) (= |v_Thread0_P0___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~z$w_buff1_used~0_1 256))) (not (= (mod v_~z$w_buff0_used~0_1 256) 0)))) 1 0)) (= v_~z$w_buff1_used~0_1 v_~z$w_buff0_used~0_2) (= v_Thread0_P0___VERIFIER_assert_~expression_1 |v_Thread0_P0___VERIFIER_assert_#in~expression_1|) (= v_~z$w_buff0_used~0_1 1) (= v_~z$w_buff1~0_1 v_~z$w_buff0~0_2)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_2, ~z$w_buff0~0=v_~z$w_buff0~0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_1, Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1, ~z$w_buff0~0=v_~z$w_buff0~0_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, Thread0_P0___VERIFIER_assert_#in~expression=|v_Thread0_P0___VERIFIER_assert_#in~expression_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_1, ~z$w_buff1~0=v_~z$w_buff1~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0___VERIFIER_assert_~expression, Thread0_P0_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, Thread0_P0_~arg.base, Thread0_P0___VERIFIER_assert_#in~expression, ~z$w_buff1_used~0, ~z$w_buff1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [536] L4-->L4-3: Formula: (not (= 0 v_Thread0_P0___VERIFIER_assert_~expression_3)) InVars {Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} OutVars{Thread0_P0___VERIFIER_assert_~expression=v_Thread0_P0___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [539] L4-3-->L719: Formula: (and (= v_~z$r_buff1_thd2~0_1 v_~z$r_buff0_thd2~0_1) (= v_~__unbuffered_p0_EAX~0_1 v_~x~0_1) (= v_~z$r_buff0_thd1~0_1 1) (= v_~z$r_buff1_thd0~0_1 v_~z$r_buff0_thd0~0_1) (= v_~z$r_buff1_thd1~0_1 v_~z$r_buff0_thd1~0_2)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_2, ~x~0=v_~x~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_1} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_1, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_1, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_1, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_1, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_1, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_1, ~x~0=v_~x~0_1, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_1} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [540] L719-->L719-5: Formula: (and (= |v_Thread0_P0_#t~ite4_1| v_~z$w_buff0~0_3) (not (= (mod v_~z$w_buff0_used~0_3 256) 0)) (not (= 0 (mod v_~z$r_buff0_thd1~0_3 256)))) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_1|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_3, ~z$w_buff0~0=v_~z$w_buff0~0_3, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [447] L782-->L782-1: Formula: (and (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t908~0.base_2|) 0) (= 0 |v_ULTIMATE.start_main_~#t908~0.offset_2|) (= |v_#valid_3| (store |v_#valid_4| |v_ULTIMATE.start_main_~#t908~0.base_2| 1)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t908~0.base_2| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t908~0.base_2|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_2|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_2|, #length=|v_#length_3|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t908~0.offset, ULTIMATE.start_main_~#t908~0.base, #valid, #length] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [448] L782-1-->L783: Formula: (= |v_#memory_int_3| (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t908~0.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t908~0.base_3|) |v_ULTIMATE.start_main_~#t908~0.offset_3| 1))) InVars {ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_3|, #memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_3|} OutVars{ULTIMATE.start_main_~#t908~0.offset=|v_ULTIMATE.start_main_~#t908~0.offset_3|, #memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t908~0.base=|v_ULTIMATE.start_main_~#t908~0.base_3|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 [647] L783-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [561] P1ENTRY-->L746: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~z$mem_tmp~0_1 v_~z~0_3) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_~z$flush_delayed~0_1 v_~weak$$choice2~0_7) (= v_~weak$$choice0~0_1 (ite (= 0 (+ |v_Thread1_P1_#t~nondet10.base_1| |v_Thread1_P1_#t~nondet10.offset_1|)) 0 1)) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_1) (= v_~x~0_2 1) (= v_~y~0_1 1) (= v_~weak$$choice2~0_7 (ite (= (+ |v_Thread1_P1_#t~nondet11.offset_1| |v_Thread1_P1_#t~nondet11.base_1|) 0) 0 1))) InVars {Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_1|, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_1|, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_1|, ~z~0=v_~z~0_3, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_#t~nondet10.base=|v_Thread1_P1_#t~nondet10.base_2|, ~z$flush_delayed~0=v_~z$flush_delayed~0_1, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, Thread1_P1_#t~nondet10.offset=|v_Thread1_P1_#t~nondet10.offset_2|, ~weak$$choice0~0=v_~weak$$choice0~0_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, Thread1_P1_#t~nondet11.base=|v_Thread1_P1_#t~nondet11.base_2|, ~z~0=v_~z~0_3, ~weak$$choice2~0=v_~weak$$choice2~0_7, ~y~0=v_~y~0_1, Thread1_P1_#t~nondet11.offset=|v_Thread1_P1_#t~nondet11.offset_2|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[~z$mem_tmp~0, Thread1_P1_~arg.offset, Thread1_P1_#t~nondet10.base, ~z$flush_delayed~0, Thread1_P1_#t~nondet10.offset, ~weak$$choice0~0, Thread1_P1_~arg.base, ~__unbuffered_p1_EAX~0, Thread1_P1_#t~nondet11.base, ~weak$$choice2~0, ~y~0, Thread1_P1_#t~nondet11.offset, ~x~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [562] L746-->L746-5: Formula: (and (let ((.cse0 (= (mod v_~z$r_buff0_thd2~0_15 256) 0))) (or (= 0 (mod v_~z$w_buff0_used~0_26 256)) (and .cse0 (= 0 (mod v_~z$r_buff1_thd2~0_9 256))) (and .cse0 (= (mod v_~z$w_buff1_used~0_17 256) 0)))) (= |v_Thread1_P1_#t~ite13_1| v_~z~0_4)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, ~z~0=v_~z~0_4, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_26, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_15, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_9} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_26, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_9, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_17, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_1|, ~z~0=v_~z~0_4, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [564] L746-5-->L747: Formula: (= v_~z~0_6 |v_Thread1_P1_#t~ite13_2|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|, ~z~0=v_~z~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, Thread1_P1_#t~ite13, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [567] L747-->L747-8: Formula: (and (= |v_Thread1_P1_#t~ite16_1| v_~z$w_buff0~0_5) (not (= (mod v_~weak$$choice2~0_8 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_8, ~z$w_buff0~0=v_~z$w_buff0~0_5} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_8, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_1|, ~z$w_buff0~0=v_~z$w_buff0~0_5} AuxVars[] AssignedVars[Thread1_P1_#t~ite16] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [570] L747-8-->L748: Formula: (= v_~z$w_buff0~0_10 |v_Thread1_P1_#t~ite16_2|) InVars {Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_2|} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_1|, Thread1_P1_#t~ite16=|v_Thread1_P1_#t~ite16_3|, ~z$w_buff0~0=v_~z$w_buff0~0_10, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_1|} AuxVars[] AssignedVars[~z$w_buff0~0, Thread1_P1_#t~ite14, Thread1_P1_#t~ite16, Thread1_P1_#t~ite15] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [573] L748-->L748-8: Formula: (and (= |v_Thread1_P1_#t~ite19_1| v_~z$w_buff1~0_5) (not (= (mod v_~weak$$choice2~0_10 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_10, ~z$w_buff1~0=v_~z$w_buff1~0_5} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_1|, ~z$w_buff1~0=v_~z$w_buff1~0_5, ~weak$$choice2~0=v_~weak$$choice2~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite19] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [578] L748-8-->L749: Formula: (= v_~z$w_buff1~0_9 |v_Thread1_P1_#t~ite19_2|) InVars {Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_2|} OutVars{Thread1_P1_#t~ite19=|v_Thread1_P1_#t~ite19_3|, ~z$w_buff1~0=v_~z$w_buff1~0_9, Thread1_P1_#t~ite18=|v_Thread1_P1_#t~ite18_1|, Thread1_P1_#t~ite17=|v_Thread1_P1_#t~ite17_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite19, ~z$w_buff1~0, Thread1_P1_#t~ite18, Thread1_P1_#t~ite17] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [582] L749-->L749-8: Formula: (and (not (= (mod v_~weak$$choice2~0_12 256) 0)) (= |v_Thread1_P1_#t~ite22_1| v_~z$w_buff0_used~0_50)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_1|, ~weak$$choice2~0=v_~weak$$choice2~0_12, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_50} AuxVars[] AssignedVars[Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [587] L749-8-->L750: Formula: (= v_~z$w_buff0_used~0_15 |v_Thread1_P1_#t~ite22_2|) InVars {Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_2|} OutVars{Thread1_P1_#t~ite22=|v_Thread1_P1_#t~ite22_3|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_15, Thread1_P1_#t~ite21=|v_Thread1_P1_#t~ite21_1|, Thread1_P1_#t~ite20=|v_Thread1_P1_#t~ite20_1|} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread1_P1_#t~ite21, Thread1_P1_#t~ite20, Thread1_P1_#t~ite22] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [591] L750-->L750-8: Formula: (and (not (= (mod v_~weak$$choice2~0_1 256) 0)) (= |v_Thread1_P1_#t~ite25_1| v_~z$w_buff1_used~0_9)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_9, ~weak$$choice2~0=v_~weak$$choice2~0_1} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_9, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[Thread1_P1_#t~ite25] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [596] L750-8-->L751: Formula: (= v_~z$w_buff1_used~0_12 |v_Thread1_P1_#t~ite25_2|) InVars {Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_2|} OutVars{Thread1_P1_#t~ite23=|v_Thread1_P1_#t~ite23_1|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_12, Thread1_P1_#t~ite25=|v_Thread1_P1_#t~ite25_3|, Thread1_P1_#t~ite24=|v_Thread1_P1_#t~ite24_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite23, ~z$w_buff1_used~0, Thread1_P1_#t~ite25, Thread1_P1_#t~ite24] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [600] L751-->L751-8: Formula: (and (= |v_Thread1_P1_#t~ite28_1| v_~z$r_buff0_thd2~0_7) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_3, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_7, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [605] L751-8-->L752: Formula: (= v_~z$r_buff0_thd2~0_12 |v_Thread1_P1_#t~ite28_2|) InVars {Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_2|} OutVars{Thread1_P1_#t~ite27=|v_Thread1_P1_#t~ite27_1|, Thread1_P1_#t~ite26=|v_Thread1_P1_#t~ite26_1|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_12, Thread1_P1_#t~ite28=|v_Thread1_P1_#t~ite28_3|} AuxVars[] AssignedVars[Thread1_P1_#t~ite27, Thread1_P1_#t~ite26, ~z$r_buff0_thd2~0, Thread1_P1_#t~ite28] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [609] L752-->L752-8: Formula: (and (= |v_Thread1_P1_#t~ite31_1| v_~z$r_buff1_thd2~0_6) (not (= 0 (mod v_~weak$$choice2~0_5 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_6} OutVars{Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_1|, ~weak$$choice2~0=v_~weak$$choice2~0_5, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_6} AuxVars[] AssignedVars[Thread1_P1_#t~ite31] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [614] L752-8-->L754: Formula: (and (= v_~__unbuffered_p1_EBX~0_1 v_~z~0_5) (= v_~z$r_buff1_thd2~0_11 |v_Thread1_P1_#t~ite31_2|)) InVars {Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_2|, ~z~0=v_~z~0_5} OutVars{~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_1, Thread1_P1_#t~ite31=|v_Thread1_P1_#t~ite31_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_11, Thread1_P1_#t~ite30=|v_Thread1_P1_#t~ite30_1|, ~z~0=v_~z~0_5, Thread1_P1_#t~ite29=|v_Thread1_P1_#t~ite29_1|} AuxVars[] AssignedVars[~__unbuffered_p1_EBX~0, Thread1_P1_#t~ite31, ~z$r_buff1_thd2~0, Thread1_P1_#t~ite30, Thread1_P1_#t~ite29] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [618] L754-->L754-2: Formula: (and (not (= (mod v_~z$flush_delayed~0_2 256) 0)) (= |v_Thread1_P1_#t~ite32_1| v_~z$mem_tmp~0_2)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_2, ~z$flush_delayed~0=v_~z$flush_delayed~0_2, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite4|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 [542] L719-5-->L720: Formula: (= v_~z~0_2 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~z~0=v_~z~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [545] L720-->L720-2: Formula: (and (= |v_Thread0_P0_#t~ite5_1| 0) (not (= 0 (mod v_~z$r_buff0_thd1~0_5 256))) (not (= (mod v_~z$w_buff0_used~0_5 256) 0))) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_5} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_1|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_5, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [548] L720-2-->L721: Formula: (= v_~z$w_buff0_used~0_7 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_7} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread0_P0_#t~ite5] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [550] L721-->L721-2: Formula: (and (or (= (mod v_~z$w_buff1_used~0_5 256) 0) (= 0 (mod v_~z$r_buff1_thd1~0_5 256))) (= |v_Thread0_P0_#t~ite6_2| v_~z$w_buff1_used~0_5) (or (= 0 (mod v_~z$w_buff0_used~0_9 256)) (= (mod v_~z$r_buff0_thd1~0_8 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_5, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_9, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_5} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_5, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_9, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_5, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [551] L721-2-->L722: Formula: (= v_~z$w_buff1_used~0_6 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_6, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [553] L722-->L722-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_11 256) 0) (= 0 (mod v_~z$r_buff0_thd1~0_10 256))) (= |v_Thread0_P0_#t~ite7_2| v_~z$r_buff0_thd1~0_10)) InVars {~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_11} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_11} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=1, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [554] L722-2-->L723: Formula: (= v_~z$r_buff0_thd1~0_11 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_11, Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite7, ~z$r_buff0_thd1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [556] L723-->L723-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd1~0_13 256)) (= (mod v_~z$w_buff0_used~0_13 256) 0)) (or (= (mod v_~z$r_buff1_thd1~0_7 256) 0) (= 0 (mod v_~z$w_buff1_used~0_8 256))) (= |v_Thread0_P0_#t~ite8_2| v_~z$r_buff1_thd1~0_7)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_13, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_7} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_8, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_13, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 [557] L723-2-->L728: Formula: (and (= v_~z$r_buff1_thd1~0_8 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_8} AuxVars[] AssignedVars[~z$r_buff1_thd1~0, ~__unbuffered_cnt~0, Thread0_P0_#t~ite8] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 [623] L754-2-->L758: Formula: (and (= v_~z~0_8 |v_Thread1_P1_#t~ite32_3|) (= v_~z$flush_delayed~0_4 0)) InVars {Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_3|} OutVars{~z$flush_delayed~0=v_~z$flush_delayed~0_4, ~z~0=v_~z~0_8, Thread1_P1_#t~ite32=|v_Thread1_P1_#t~ite32_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite32, ~z$flush_delayed~0, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [626] L758-->L758-2: Formula: (or (= 0 (mod v_~z$r_buff0_thd2~0_24 256)) (= (mod v_~z$w_buff0_used~0_35 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_24} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_35, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_24} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [629] L758-2-->L758-4: Formula: (and (= |v_Thread1_P1_#t~ite33_3| v_~z~0_9) (or (= 0 (mod v_~z$r_buff1_thd2~0_15 256)) (= 0 (mod v_~z$w_buff1_used~0_22 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_22, ~z~0=v_~z~0_9, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_15} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_22, Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_3|, ~z~0=v_~z~0_9, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_15} AuxVars[] AssignedVars[Thread1_P1_#t~ite33] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [632] L758-4-->L758-5: Formula: (= |v_Thread1_P1_#t~ite34_4| |v_Thread1_P1_#t~ite33_4|) InVars {Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_4|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite34] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite33|=0, |Thread1_P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [627] L758-5-->L759: Formula: (= v_~z~0_10 |v_Thread1_P1_#t~ite34_2|) InVars {Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_2|} OutVars{Thread1_P1_#t~ite33=|v_Thread1_P1_#t~ite33_1|, Thread1_P1_#t~ite34=|v_Thread1_P1_#t~ite34_3|, ~z~0=v_~z~0_10} AuxVars[] AssignedVars[Thread1_P1_#t~ite33, Thread1_P1_#t~ite34, ~z~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [631] L759-->L759-2: Formula: (and (= |v_Thread1_P1_#t~ite35_2| v_~z$w_buff0_used~0_39) (or (= 0 (mod v_~z$r_buff0_thd2~0_28 256)) (= 0 (mod v_~z$w_buff0_used~0_39 256)))) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_39, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_28} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_39, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_28} AuxVars[] AssignedVars[Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [633] L759-2-->L760: Formula: (= v_~z$w_buff0_used~0_40 |v_Thread1_P1_#t~ite35_3|) InVars {Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_3|} OutVars{Thread1_P1_#t~ite35=|v_Thread1_P1_#t~ite35_4|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_40} AuxVars[] AssignedVars[~z$w_buff0_used~0, Thread1_P1_#t~ite35] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [635] L760-->L760-2: Formula: (and (= |v_Thread1_P1_#t~ite36_2| v_~z$w_buff1_used~0_26) (or (= 0 (mod v_~z$w_buff1_used~0_26 256)) (= (mod v_~z$r_buff1_thd2~0_19 256) 0)) (or (= (mod v_~z$r_buff0_thd2~0_32 256) 0) (= 0 (mod v_~z$w_buff0_used~0_44 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_44, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_19} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_26, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_2|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_44, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_19} AuxVars[] AssignedVars[Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [636] L760-2-->L761: Formula: (= v_~z$w_buff1_used~0_27 |v_Thread1_P1_#t~ite36_3|) InVars {Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_3|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_27, Thread1_P1_#t~ite36=|v_Thread1_P1_#t~ite36_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, Thread1_P1_#t~ite36] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [638] L761-->L761-2: Formula: (and (or (= 0 (mod v_~z$r_buff0_thd2~0_36 256)) (= 0 (mod v_~z$w_buff0_used~0_48 256))) (= |v_Thread1_P1_#t~ite37_2| v_~z$r_buff0_thd2~0_36)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_36} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_36, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_2|} AuxVars[] AssignedVars[Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [639] L761-2-->L762: Formula: (= v_~z$r_buff0_thd2~0_37 |v_Thread1_P1_#t~ite37_3|) InVars {Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_3|} OutVars{~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_37, Thread1_P1_#t~ite37=|v_Thread1_P1_#t~ite37_4|} AuxVars[] AssignedVars[~z$r_buff0_thd2~0, Thread1_P1_#t~ite37] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [641] L762-->L762-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_51 256) 0) (= (mod v_~z$r_buff0_thd2~0_39 256) 0)) (or (= (mod v_~z$w_buff1_used~0_29 256) 0) (= (mod v_~z$r_buff1_thd2~0_21 256) 0)) (= |v_Thread1_P1_#t~ite38_2| v_~z$r_buff1_thd2~0_21)) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_51, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_39, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_29, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_51, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_39, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_21, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_2|} AuxVars[] AssignedVars[Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 [642] L762-2-->L767: Formula: (and (= v_~z$r_buff1_thd2~0_22 |v_Thread1_P1_#t~ite38_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_3|} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_22, Thread1_P1_#t~ite38=|v_Thread1_P1_#t~ite38_4|} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite38] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [384] L783-1-->L787: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_5 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5, ULTIMATE.start_main_#t~nondet41=|v_ULTIMATE.start_main_#t~nondet41_2|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet41, ~main$tmp_guard0~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [478] L787-->L789: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [361] L789-->L789-2: Formula: (or (= (mod v_~z$w_buff0_used~0_57 256) 0) (= (mod v_~z$r_buff0_thd0~0_4 256) 0)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_57, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_4} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_57, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_4} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [527] L789-2-->L789-4: Formula: (and (= |v_ULTIMATE.start_main_#t~ite42_3| v_~z~0_12) (or (= (mod v_~z$r_buff1_thd0~0_4 256) 0) (= 0 (mod v_~z$w_buff1_used~0_34 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_34, ~z~0=v_~z~0_12, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_4} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_34, ~z~0=v_~z~0_12, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_3|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_4} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [531] L789-4-->L789-5: Formula: (= |v_ULTIMATE.start_main_#t~ite43_3| |v_ULTIMATE.start_main_#t~ite42_4|) InVars {ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} OutVars{ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [532] L789-5-->L790: Formula: (= v_~z~0_13 |v_ULTIMATE.start_main_#t~ite43_5|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|} OutVars{~z~0=v_~z~0_13, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|} AuxVars[] AssignedVars[~z~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [471] L790-->L790-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_59 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_6 256))) (= |v_ULTIMATE.start_main_#t~ite44_3| v_~z$w_buff0_used~0_59)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_6} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_6, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_59, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [458] L790-2-->L791: Formula: (= v_~z$w_buff0_used~0_60 |v_ULTIMATE.start_main_#t~ite44_5|) InVars {ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|} OutVars{~z$w_buff0_used~0=v_~z$w_buff0_used~0_60, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[~z$w_buff0_used~0, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [409] L791-->L791-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite45_3| v_~z$w_buff1_used~0_36) (or (= (mod v_~z$w_buff0_used~0_62 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_8 256))) (or (= (mod v_~z$w_buff1_used~0_36 256) 0) (= 0 (mod v_~z$r_buff1_thd0~0_6 256)))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_36, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_62, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_6} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_36, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_8, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_62, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [415] L791-2-->L792: Formula: (= v_~z$w_buff1_used~0_37 |v_ULTIMATE.start_main_#t~ite45_5|) InVars {ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|} OutVars{~z$w_buff1_used~0=v_~z$w_buff1_used~0_37, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|} AuxVars[] AssignedVars[~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite45] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [510] L792-->L792-2: Formula: (and (or (= (mod v_~z$w_buff0_used~0_64 256) 0) (= 0 (mod v_~z$r_buff0_thd0~0_10 256))) (= |v_ULTIMATE.start_main_#t~ite46_3| v_~z$r_buff0_thd0~0_10)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_64, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_10, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_64} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [516] L792-2-->L793: Formula: (= v_~z$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite46_5|) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_11} AuxVars[] AssignedVars[~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [446] L793-->L793-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_3| v_~z$r_buff1_thd0~0_8) (or (= 0 (mod v_~z$r_buff1_thd0~0_8 256)) (= (mod v_~z$w_buff1_used~0_39 256) 0)) (or (= 0 (mod v_~z$r_buff0_thd0~0_13 256)) (= (mod v_~z$w_buff0_used~0_66 256) 0))) InVars {~z$w_buff1_used~0=v_~z$w_buff1_used~0_39, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_39, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_13, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_66, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [451] L793-2-->L798: Formula: (and (= v_~z$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite47_5|) (= v_~main$tmp_guard1~0_2 (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EBX~0_2) (= 1 v_~__unbuffered_p1_EAX~0_2) (= v_~__unbuffered_p0_EAX~0_2 0))) 1 0) 0) 0 1))) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_2, ~__unbuffered_p1_EBX~0=v_~__unbuffered_p1_EBX~0_2, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_9, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} AuxVars[] AssignedVars[~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite47, ~main$tmp_guard1~0] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [476] L798-->L798-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_3 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [479] L798-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [407] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [404] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 [402] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0___VERIFIER_assert_~expression=1, Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0___VERIFIER_assert_#in~expression|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); srcloc: L780-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff0_thd1~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite4 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); srcloc: L782 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); srcloc: L782-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 1;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite13 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite14;havoc #t~ite15; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1~0 := #t~ite19;havoc #t~ite17;havoc #t~ite19;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite22;havoc #t~ite20; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite28;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite31;havoc #t~ite29;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~z$flush_delayed~0 % 256;#t~ite32 := ~z$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite6 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256);#t~ite7 := ~z$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite8 := ~z$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 ~z~0 := #t~ite32;havoc #t~ite32;~z$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256);#t~ite33 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite34;havoc #t~ite33;havoc #t~ite34; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite35 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite36 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite37 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite38 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite42 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite44 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite45 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~z~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [?] -1 ~z$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [?] -1 ~z$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [?] -1 ~z$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [?] -1 ~z$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [?] -1 ~z$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); srcloc: L780 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); srcloc: L780-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~z$w_buff1~0 := ~z$w_buff0~0;~z$w_buff0~0 := 1;~z$w_buff1_used~0 := ~z$w_buff0_used~0;~z$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0;~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0;~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0;~z$r_buff0_thd1~0 := 1;~__unbuffered_p0_EAX~0 := ~x~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite4 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); srcloc: L782 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); srcloc: L782-1 VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x~0 := 1;~y~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0;~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1);havoc #t~nondet10.base, #t~nondet10.offset;~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1);havoc #t~nondet11.base, #t~nondet11.offset;~z$flush_delayed~0 := ~weak$$choice2~0;~z$mem_tmp~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256);#t~ite13 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite13;havoc #t~ite12;havoc #t~ite13; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite16 := ~z$w_buff0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite16|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0~0 := #t~ite16;havoc #t~ite16;havoc #t~ite14;havoc #t~ite15; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite19 := ~z$w_buff1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite19|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1~0 := #t~ite19;havoc #t~ite17;havoc #t~ite19;havoc #t~ite18; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite22 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite22|=1, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite22;havoc #t~ite21;havoc #t~ite22;havoc #t~ite20; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite25 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite25|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite25;havoc #t~ite25;havoc #t~ite24;havoc #t~ite23; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite28 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite28|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite28;havoc #t~ite28;havoc #t~ite27;havoc #t~ite26; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~weak$$choice2~0 % 256;#t~ite31 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite31|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite31;havoc #t~ite30;havoc #t~ite31;havoc #t~ite29;~__unbuffered_p1_EBX~0 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume 0 != ~z$flush_delayed~0 % 256;#t~ite32 := ~z$mem_tmp~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite4|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 0 ~z~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256;#t~ite5 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite6 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256);#t~ite7 := ~z$r_buff0_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=1, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256));#t~ite8 := ~z$r_buff1_thd1~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 0 ~z$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite32|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [?] 1 ~z~0 := #t~ite32;havoc #t~ite32;~z$flush_delayed~0 := 0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256);#t~ite33 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 #t~ite34 := #t~ite33; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite33|=0, |P1_#t~ite34|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z~0 := #t~ite34;havoc #t~ite33;havoc #t~ite34; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite35 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite35|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff0_used~0 := #t~ite35;havoc #t~ite35; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite36 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite36|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$w_buff1_used~0 := #t~ite36;havoc #t~ite36; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256);#t~ite37 := ~z$r_buff0_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite37|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff0_thd2~0 := #t~ite37;havoc #t~ite37; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256));#t~ite38 := ~z$r_buff1_thd2~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite38|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] 1 ~z$r_buff1_thd2~0 := #t~ite38;havoc #t~ite38;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet41;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256);main_#t~ite42 := ~z~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 main_#t~ite43 := main_#t~ite42; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite42|=0, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite43; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite44 := ~z$w_buff0_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite44|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff0_used~0 := main_#t~ite44;havoc main_#t~ite44; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite45 := ~z$w_buff1_used~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite45|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$w_buff1_used~0 := main_#t~ite45;havoc main_#t~ite45; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256);main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff0_thd0~0 := main_#t~ite46;havoc main_#t~ite46; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256));main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_#t~ite47|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 ~z$r_buff1_thd0~0 := main_#t~ite47;havoc main_#t~ite47;~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 assume !false; VAL [P0___VERIFIER_assert_~expression=1, P0_~arg.base=0, P0_~arg.offset=0, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0___VERIFIER_assert_#in~expression|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t907~0.base|=5, |ULTIMATE.start_main_~#t907~0.offset|=0, |ULTIMATE.start_main_~#t908~0.base|=6, |ULTIMATE.start_main_~#t908~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] -1 call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] -1 call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L742] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L743] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 assume 0 != ~weak$$choice2~0 % 256; [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 assume 0 != ~weak$$choice2~0 % 256; [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] 1 assume 0 != ~z$flush_delayed~0 % 256; [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L720] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256); [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256); [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0.base, ~z$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0.base, main_~#t907~0.offset, main_~#t908~0.base, main_~#t908~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] -1 call main_~#t907~0.base, main_~#t907~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 call write~int(0, main_~#t907~0.base, main_~#t907~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] -1 call main_~#t908~0.base, main_~#t908~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 call write~int(1, main_~#t908~0.base, main_~#t908~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10.base + #t~nondet10.offset then 0 else 1); [L742] 1 havoc #t~nondet10.base, #t~nondet10.offset; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11.base + #t~nondet11.offset then 0 else 1); [L743] 1 havoc #t~nondet11.base, #t~nondet11.offset; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 assume (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256); [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 assume 0 != ~weak$$choice2~0 % 256; [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 assume 0 != ~weak$$choice2~0 % 256; [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 assume 0 != ~weak$$choice2~0 % 256; [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 assume 0 != ~weak$$choice2~0 % 256; [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 assume 0 != ~weak$$choice2~0 % 256; [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 assume 0 != ~weak$$choice2~0 % 256; [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] 1 assume 0 != ~z$flush_delayed~0 % 256; [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 assume 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256; [L720] 0 #t~ite5 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256); [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)); [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256); [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256); [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)); [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 assume !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256); [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 assume !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256); [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 assume !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)); [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0.base=5, main_~#t907~0.offset=0, main_~#t908~0.base=6, main_~#t908~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0.base=0, ~z$read_delayed_var~0.offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0, main_~#t908~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call main_~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, main_~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call main_~#t908~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, main_~#t908~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 havoc main_#t~nondet40, main_#t~nondet41, main_#t~ite43, main_#t~ite42, main_#t~ite44, main_#t~ite45, main_#t~ite46, main_#t~ite47, main_~#t907~0, main_~#t908~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call main_~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, main_~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc main_#t~nondet40; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L709] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$w_buff0_used~0 % 256) then 1 else 0); [L709] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call main_~#t908~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, main_~#t908~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite5=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite7=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc main_#t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 main_#t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 main_#t~ite43 := main_#t~ite42; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite42=0, main_#t~ite43=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := main_#t~ite43; [L789] -1 havoc main_#t~ite42; [L789] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 main_#t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite44=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := main_#t~ite44; [L790] -1 havoc main_#t~ite44; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 main_#t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite45=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := main_#t~ite45; [L791] -1 havoc main_#t~ite45; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 main_#t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := main_#t~ite46; [L792] -1 havoc main_#t~ite46; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 main_#t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=0, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := main_#t~ite47; [L793] -1 havoc main_#t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L798] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t907~0!base=5, main_~#t907~0!offset=0, main_~#t908~0!base=6, main_~#t908~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call ~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, ~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call ~#t908~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, ~#t908~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc #t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 #t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := #t~ite43; [L789] -1 havoc #t~ite42; [L789] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 #t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := #t~ite44; [L790] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := #t~ite45; [L791] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 #t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := #t~ite46; [L792] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 #t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := #t~ite47; [L793] -1 havoc #t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p0_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0] [L675] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0] [L677] -1 ~__unbuffered_p1_EBX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0] [L678] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0] [L679] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L681] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L683] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0] [L685] -1 ~z~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z~0=0] [L686] -1 ~z$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z~0=0] [L687] -1 ~z$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z~0=0] [L688] -1 ~z$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z~0=0] [L689] -1 ~z$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z~0=0] [L690] -1 ~z$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z~0=0] [L691] -1 ~z$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z~0=0] [L692] -1 ~z$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z~0=0] [L693] -1 ~z$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z~0=0] [L694] -1 ~z$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed~0=0, ~z~0=0] [L695] -1 ~z$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z~0=0] [L696] -1 ~z$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0~0=0, ~z~0=0] [L697] -1 ~z$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z~0=0] [L698] -1 ~z$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1~0=0, ~z~0=0] [L699] -1 ~z$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L700] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L701] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L780] FCALL -1 call ~#t907~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FCALL -1 call write~int(0, ~#t907~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L781] -1 havoc #t~nondet40; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=0, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L702-L729] 0 ~arg := #in~arg; [L705] 0 ~z$w_buff1~0 := ~z$w_buff0~0; [L706] 0 ~z$w_buff0~0 := 1; [L707] 0 ~z$w_buff1_used~0 := ~z$w_buff0_used~0; [L708] 0 ~z$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=0, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L710] 0 ~z$r_buff1_thd0~0 := ~z$r_buff0_thd0~0; [L711] 0 ~z$r_buff1_thd1~0 := ~z$r_buff0_thd1~0; [L712] 0 ~z$r_buff1_thd2~0 := ~z$r_buff0_thd2~0; [L713] 0 ~z$r_buff0_thd1~0 := 1; [L716] 0 ~__unbuffered_p0_EAX~0 := ~x~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L719] 0 #t~ite4 := ~z$w_buff0~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L782] FCALL -1 call ~#t908~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FCALL -1 call write~int(1, ~#t908~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=0, ~__unbuffered_p1_EBX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x~0=0, ~y~0=0, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L730-L768] 1 ~arg := #in~arg; [L733] 1 ~x~0 := 1; [L736] 1 ~y~0 := 1; [L739] 1 ~__unbuffered_p1_EAX~0 := ~y~0; [L742] 1 ~weak$$choice0~0 := (if 0 == #t~nondet10!base + #t~nondet10!offset then 0 else 1); [L742] 1 havoc #t~nondet10; [L743] 1 ~weak$$choice2~0 := (if 0 == #t~nondet11!base + #t~nondet11!offset then 0 else 1); [L743] 1 havoc #t~nondet11; [L744] 1 ~z$flush_delayed~0 := ~weak$$choice2~0; [L745] 1 ~z$mem_tmp~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] COND TRUE 1 (0 == ~z$w_buff0_used~0 % 256 || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$w_buff1_used~0 % 256)) || (0 == ~z$r_buff0_thd2~0 % 256 && 0 == ~z$r_buff1_thd2~0 % 256) [L746] 1 #t~ite13 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L746] 1 ~z~0 := #t~ite13; [L746] 1 havoc #t~ite12; [L746] 1 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L747] 1 #t~ite16 := ~z$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite16=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L747] 1 ~z$w_buff0~0 := #t~ite16; [L747] 1 havoc #t~ite16; [L747] 1 havoc #t~ite14; [L747] 1 havoc #t~ite15; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L748] 1 #t~ite19 := ~z$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite19=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L748] 1 ~z$w_buff1~0 := #t~ite19; [L748] 1 havoc #t~ite17; [L748] 1 havoc #t~ite19; [L748] 1 havoc #t~ite18; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L749] 1 #t~ite22 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite22=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L749] 1 ~z$w_buff0_used~0 := #t~ite22; [L749] 1 havoc #t~ite21; [L749] 1 havoc #t~ite22; [L749] 1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L750] 1 #t~ite25 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite25=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L750] 1 ~z$w_buff1_used~0 := #t~ite25; [L750] 1 havoc #t~ite25; [L750] 1 havoc #t~ite24; [L750] 1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L751] 1 #t~ite28 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite28=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L751] 1 ~z$r_buff0_thd2~0 := #t~ite28; [L751] 1 havoc #t~ite28; [L751] 1 havoc #t~ite27; [L751] 1 havoc #t~ite26; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] COND TRUE 1 0 != ~weak$$choice2~0 % 256 [L752] 1 #t~ite31 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite31=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L752] 1 ~z$r_buff1_thd2~0 := #t~ite31; [L752] 1 havoc #t~ite30; [L752] 1 havoc #t~ite31; [L752] 1 havoc #t~ite29; [L753] 1 ~__unbuffered_p1_EBX~0 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L754] COND TRUE 1 0 != ~z$flush_delayed~0 % 256 [L754] 1 #t~ite32 := ~z$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L719] 0 ~z~0 := #t~ite4; [L719] 0 havoc #t~ite3; [L719] 0 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] COND TRUE 0 0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256 [L720] 0 #t~ite5 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=1, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L720] 0 ~z$w_buff0_used~0 := #t~ite5; [L720] 0 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L721] 0 #t~ite6 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L721] 0 ~z$w_buff1_used~0 := #t~ite6; [L721] 0 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] COND FALSE 0 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) [L722] 0 #t~ite7 := ~z$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L722] 0 ~z$r_buff0_thd1~0 := #t~ite7; [L722] 0 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] COND FALSE 0 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd1~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd1~0 % 256)) [L723] 0 #t~ite8 := ~z$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L723] 0 ~z$r_buff1_thd1~0 := #t~ite8; [L723] 0 havoc #t~ite8; [L726] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite32=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=1, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=1] [L754] 1 ~z~0 := #t~ite32; [L754] 1 havoc #t~ite32; [L755] 1 ~z$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] COND FALSE 1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256) [L758] 1 #t~ite33 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 #t~ite34 := #t~ite33; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite33=0, #t~ite34=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L758] 1 ~z~0 := #t~ite34; [L758] 1 havoc #t~ite33; [L758] 1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L759] 1 #t~ite35 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite35=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L759] 1 ~z$w_buff0_used~0 := #t~ite35; [L759] 1 havoc #t~ite35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L760] 1 #t~ite36 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite36=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L760] 1 ~z$w_buff1_used~0 := #t~ite36; [L760] 1 havoc #t~ite36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] COND FALSE 1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) [L761] 1 #t~ite37 := ~z$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite37=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L761] 1 ~z$r_buff0_thd2~0 := #t~ite37; [L761] 1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] COND FALSE 1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd2~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd2~0 % 256)) [L762] 1 #t~ite38 := ~z$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite38=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L762] 1 ~z$r_buff1_thd2~0 := #t~ite38; [L762] 1 havoc #t~ite38; [L765] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L783] -1 havoc #t~nondet41; [L785] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L787] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] COND FALSE -1 !(0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256) [L789] -1 #t~ite42 := ~z~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 #t~ite43 := #t~ite42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L789] -1 ~z~0 := #t~ite43; [L789] -1 havoc #t~ite42; [L789] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L790] -1 #t~ite44 := ~z$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L790] -1 ~z$w_buff0_used~0 := #t~ite44; [L790] -1 havoc #t~ite44; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L791] -1 #t~ite45 := ~z$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L791] -1 ~z$w_buff1_used~0 := #t~ite45; [L791] -1 havoc #t~ite45; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] COND FALSE -1 !(0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) [L792] -1 #t~ite46 := ~z$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L792] -1 ~z$r_buff0_thd0~0 := #t~ite46; [L792] -1 havoc #t~ite46; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] COND FALSE -1 !((0 != ~z$w_buff0_used~0 % 256 && 0 != ~z$r_buff0_thd0~0 % 256) || (0 != ~z$w_buff1_used~0 % 256 && 0 != ~z$r_buff1_thd0~0 % 256)) [L793] -1 #t~ite47 := ~z$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L793] -1 ~z$r_buff1_thd0~0 := #t~ite47; [L793] -1 havoc #t~ite47; [L796] -1 ~main$tmp_guard1~0 := (if 0 == (if !((0 == ~__unbuffered_p0_EAX~0 && 1 == ~__unbuffered_p1_EAX~0) && 0 == ~__unbuffered_p1_EBX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p0_EAX~0=0, ~__unbuffered_p1_EAX~0=1, ~__unbuffered_p1_EBX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x~0=1, ~y~0=1, ~z$flush_delayed~0=0, ~z$mem_tmp~0=0, ~z$r_buff0_thd0~0=0, ~z$r_buff0_thd1~0=1, ~z$r_buff0_thd2~0=0, ~z$r_buff1_thd0~0=0, ~z$r_buff1_thd1~0=0, ~z$r_buff1_thd2~0=0, ~z$read_delayed_var~0!base=0, ~z$read_delayed_var~0!offset=0, ~z$read_delayed~0=0, ~z$w_buff0_used~0=0, ~z$w_buff0~0=1, ~z$w_buff1_used~0=0, ~z$w_buff1~0=0, ~z~0=0] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L677] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L679] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L681] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L683] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L685] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L686] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L687] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L688] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L689] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L690] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L691] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0] [L692] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L693] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L694] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0] [L695] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L696] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L697] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L698] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L699] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L700] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L701] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L780] -1 pthread_t t907; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L781] FCALL, FORK -1 pthread_create(&t907, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L705] 0 z$w_buff1 = z$w_buff0 [L706] 0 z$w_buff0 = 1 [L707] 0 z$w_buff1_used = z$w_buff0_used [L708] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L710] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L711] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L712] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L713] 0 z$r_buff0_thd1 = (_Bool)1 [L716] 0 __unbuffered_p0_EAX = x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L782] -1 pthread_t t908; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L783] FCALL, FORK -1 pthread_create(&t908, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L733] 1 x = 1 [L736] 1 y = 1 [L739] 1 __unbuffered_p1_EAX = y [L742] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L743] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L744] 1 z$flush_delayed = weak$$choice2 [L745] 1 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] EXPR 1 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] 1 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L747] EXPR 1 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L747] 1 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L748] EXPR 1 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L748] 1 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L749] EXPR 1 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L749] 1 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L750] EXPR 1 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] 1 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] EXPR 1 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L751] 1 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L752] EXPR 1 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L752] 1 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L753] 1 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L754] EXPR 1 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] 0 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L720] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L720] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L721] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L721] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L722] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L722] 0 z$r_buff0_thd1 = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 [L723] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L723] 0 z$r_buff1_thd1 = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 [L726] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L754] 1 z = z$flush_delayed ? z$mem_tmp : z [L755] 1 z$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] 1 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L759] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L759] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L760] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L760] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L761] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L761] 1 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L762] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L762] 1 z$r_buff1_thd2 = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 [L765] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L785] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L790] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L790] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L791] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L791] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L792] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L792] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L793] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L793] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L796] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] ----- [2018-11-22 23:47:21,700 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_83e09c86-6c59-4bed-8864-ac2521e4f4d8/bin-2019/utaipan/witness.graphml [2018-11-22 23:47:21,700 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 23:47:21,701 INFO L168 Benchmark]: Toolchain (without parser) took 24385.53 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 957.6 MB in the beginning and 1.4 GB in the end (delta: -399.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,702 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 23:47:21,702 INFO L168 Benchmark]: CACSL2BoogieTranslator took 412.89 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -165.1 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,703 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.01 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,703 INFO L168 Benchmark]: Boogie Preprocessor took 26.46 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 23:47:21,703 INFO L168 Benchmark]: RCFGBuilder took 524.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.4 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,704 INFO L168 Benchmark]: TraceAbstraction took 18776.79 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -414.5 MB). Peak memory consumption was 986.4 MB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,704 INFO L168 Benchmark]: Witness Printer took 4601.72 ms. Allocated memory is still 2.6 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 127.2 MB). Peak memory consumption was 127.2 MB. Max. memory is 11.5 GB. [2018-11-22 23:47:21,706 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 412.89 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -165.1 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.01 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.46 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 524.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.4 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 18776.79 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: -414.5 MB). Peak memory consumption was 986.4 MB. Max. memory is 11.5 GB. * Witness Printer took 4601.72 ms. Allocated memory is still 2.6 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 127.2 MB). Peak memory consumption was 127.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L675] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0] [L677] -1 int __unbuffered_p1_EBX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0] [L678] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0] [L679] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L681] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L683] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L685] -1 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0] [L686] -1 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0] [L687] -1 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0] [L688] -1 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L689] -1 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L690] -1 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L691] -1 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0] [L692] -1 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L693] -1 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L694] -1 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0] [L695] -1 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L696] -1 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L697] -1 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L698] -1 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L699] -1 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L700] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L701] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L780] -1 pthread_t t907; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L781] FCALL, FORK -1 pthread_create(&t907, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L705] 0 z$w_buff1 = z$w_buff0 [L706] 0 z$w_buff0 = 1 [L707] 0 z$w_buff1_used = z$w_buff0_used [L708] 0 z$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L710] 0 z$r_buff1_thd0 = z$r_buff0_thd0 [L711] 0 z$r_buff1_thd1 = z$r_buff0_thd1 [L712] 0 z$r_buff1_thd2 = z$r_buff0_thd2 [L713] 0 z$r_buff0_thd1 = (_Bool)1 [L716] 0 __unbuffered_p0_EAX = x VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L782] -1 pthread_t t908; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L783] FCALL, FORK -1 pthread_create(&t908, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=0, __unbuffered_p1_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L733] 1 x = 1 [L736] 1 y = 1 [L739] 1 __unbuffered_p1_EAX = y [L742] 1 weak$$choice0 = __VERIFIER_nondet_pointer() [L743] 1 weak$$choice2 = __VERIFIER_nondet_pointer() [L744] 1 z$flush_delayed = weak$$choice2 [L745] 1 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] EXPR 1 !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L746] 1 z = !z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff1) [L747] EXPR 1 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L747] 1 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : z$w_buff0)) [L748] EXPR 1 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L748] 1 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff1 : z$w_buff1)) [L749] EXPR 1 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L749] 1 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used)) [L750] EXPR 1 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L750] 1 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L751] EXPR 1 weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L751] 1 z$r_buff0_thd2 = weak$$choice2 ? z$r_buff0_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff0_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2)) [L752] EXPR 1 weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L752] 1 z$r_buff1_thd2 = weak$$choice2 ? z$r_buff1_thd2 : (!z$w_buff0_used || !z$r_buff0_thd2 && !z$w_buff1_used || !z$r_buff0_thd2 && !z$r_buff1_thd2 ? z$r_buff1_thd2 : (z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : (_Bool)0)) [L753] 1 __unbuffered_p1_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L754] EXPR 1 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L719] 0 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L720] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L720] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L721] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L721] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L722] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L722] 0 z$r_buff0_thd1 = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1 [L723] EXPR 0 z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L723] 0 z$r_buff1_thd1 = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$r_buff1_thd1 [L726] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=1, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L754] 1 z = z$flush_delayed ? z$mem_tmp : z [L755] 1 z$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] EXPR 1 z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z)=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L758] 1 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L759] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L759] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L760] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L760] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L761] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L761] 1 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L762] EXPR 1 z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L762] 1 z$r_buff1_thd2 = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$r_buff1_thd2 [L765] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L785] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L789] -1 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L790] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L790] -1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L791] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L791] -1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L792] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L792] -1 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L793] EXPR -1 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L793] -1 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L796] -1 main$tmp_guard1 = !(__unbuffered_p0_EAX == 0 && __unbuffered_p1_EAX == 1 && __unbuffered_p1_EBX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p1_EAX=1, __unbuffered_p1_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 224 locations, 3 error locations. UNSAFE Result, 18.6s OverallTime, 30 OverallIterations, 1 TraceHistogramMax, 8.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 7822 SDtfs, 8844 SDslu, 17647 SDs, 0 SdLazy, 7467 SolverSat, 373 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 301 GetRequests, 72 SyntacticMatches, 35 SemanticMatches, 194 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 223 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34808occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 4.3s AutomataMinimizationTime, 29 MinimizatonAttempts, 64424 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 2274 NumberOfCodeBlocks, 2274 NumberOfCodeBlocksAsserted, 30 NumberOfCheckSat, 2148 ConstructedInterpolants, 0 QuantifiedInterpolants, 451938 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 29 InterpolantComputations, 29 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...