./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix054_tso.opt_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix054_tso.opt_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 27f95b3de1a07a1536a44b1abfe1ed78fe2c2e10 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 05:46:46,510 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 05:46:46,511 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 05:46:46,517 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 05:46:46,517 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 05:46:46,518 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 05:46:46,519 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 05:46:46,520 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 05:46:46,521 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 05:46:46,522 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 05:46:46,522 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 05:46:46,523 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 05:46:46,523 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 05:46:46,524 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 05:46:46,524 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 05:46:46,525 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 05:46:46,525 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 05:46:46,526 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 05:46:46,528 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 05:46:46,528 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 05:46:46,529 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 05:46:46,530 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 05:46:46,532 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 05:46:46,532 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:46:46,532 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:46:46,533 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:46:46,534 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:46:46,535 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:46:46,535 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:46:46,536 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:46:46,536 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:46:46,536 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:46:46,537 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:46:46,537 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:46:46,537 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:46:46,538 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:46:46,538 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-23 05:46:46,547 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:46:46,547 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:46:46,548 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 05:46:46,548 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 05:46:46,548 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 05:46:46,549 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 05:46:46,549 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 05:46:46,549 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 05:46:46,551 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:46:46,551 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:46:46,552 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:46:46,552 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:46,553 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:46:46,553 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 05:46:46,554 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:46:46,554 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 05:46:46,554 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 05:46:46,554 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 27f95b3de1a07a1536a44b1abfe1ed78fe2c2e10 [2018-11-23 05:46:46,578 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:46:46,588 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:46:46,590 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:46:46,591 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:46:46,592 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:46:46,592 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/../../sv-benchmarks/c/pthread-wmm/mix054_tso.opt_false-unreach-call.i [2018-11-23 05:46:46,639 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/data/ae8ad6563/042b97e40aa74817a4bd860c19372441/FLAG0ebcb6919 [2018-11-23 05:46:47,089 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:46:47,089 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/sv-benchmarks/c/pthread-wmm/mix054_tso.opt_false-unreach-call.i [2018-11-23 05:46:47,100 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/data/ae8ad6563/042b97e40aa74817a4bd860c19372441/FLAG0ebcb6919 [2018-11-23 05:46:47,110 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/data/ae8ad6563/042b97e40aa74817a4bd860c19372441 [2018-11-23 05:46:47,113 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:46:47,114 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:46:47,115 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:47,115 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:46:47,118 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:46:47,119 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,121 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4c5111b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47, skipping insertion in model container [2018-11-23 05:46:47,122 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,130 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:46:47,165 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:46:47,404 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:47,414 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:46:47,503 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:46:47,542 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:46:47,543 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47 WrapperNode [2018-11-23 05:46:47,543 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:46:47,544 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:47,544 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:46:47,544 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:46:47,551 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,561 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,578 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:46:47,578 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:46:47,578 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:46:47,579 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:46:47,585 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,585 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,588 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,588 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,593 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,595 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,597 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... [2018-11-23 05:46:47,599 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:46:47,599 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:46:47,600 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:46:47,600 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:46:47,600 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:46:47,632 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2018-11-23 05:46:47,633 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2018-11-23 05:46:47,633 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2018-11-23 05:46:47,633 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2018-11-23 05:46:47,634 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:46:47,634 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:46:47,635 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 05:46:48,048 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:46:48,049 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 05:46:48,049 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:48 BoogieIcfgContainer [2018-11-23 05:46:48,049 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:46:48,049 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 05:46:48,050 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 05:46:48,051 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 05:46:48,052 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 05:46:47" (1/3) ... [2018-11-23 05:46:48,052 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@241c0c68 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:48, skipping insertion in model container [2018-11-23 05:46:48,052 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:46:47" (2/3) ... [2018-11-23 05:46:48,052 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@241c0c68 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:46:48, skipping insertion in model container [2018-11-23 05:46:48,053 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:48" (3/3) ... [2018-11-23 05:46:48,054 INFO L112 eAbstractionObserver]: Analyzing ICFG mix054_tso.opt_false-unreach-call.i [2018-11-23 05:46:48,079 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,079 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,079 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,079 WARN L317 ript$VariableManager]: TermVariabe Thread0_P0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,080 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,083 WARN L317 ript$VariableManager]: TermVariabe |Thread0_P0_#t~nondet9.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,084 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe Thread1_P1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,085 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,086 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,087 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,089 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,089 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,089 WARN L317 ript$VariableManager]: TermVariabe |Thread1_P1_#t~nondet16.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 05:46:48,095 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 05:46:48,095 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 05:46:48,102 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2018-11-23 05:46:48,114 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2018-11-23 05:46:48,130 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 05:46:48,130 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 05:46:48,130 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 05:46:48,131 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 05:46:48,131 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 05:46:48,131 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 05:46:48,131 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 05:46:48,131 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 05:46:48,141 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 141places, 179 transitions [2018-11-23 05:46:49,422 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 25087 states. [2018-11-23 05:46:49,424 INFO L276 IsEmpty]: Start isEmpty. Operand 25087 states. [2018-11-23 05:46:49,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-11-23 05:46:49,430 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:49,431 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:49,432 INFO L423 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:49,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:49,436 INFO L82 PathProgramCache]: Analyzing trace with hash -1104590460, now seen corresponding path program 1 times [2018-11-23 05:46:49,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:49,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:49,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:49,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:49,473 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:49,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:49,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:49,604 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:49,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 05:46:49,604 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:49,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 05:46:49,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 05:46:49,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:49,618 INFO L87 Difference]: Start difference. First operand 25087 states. Second operand 4 states. [2018-11-23 05:46:50,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:50,184 INFO L93 Difference]: Finished difference Result 45387 states and 177625 transitions. [2018-11-23 05:46:50,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 05:46:50,186 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2018-11-23 05:46:50,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:50,413 INFO L225 Difference]: With dead ends: 45387 [2018-11-23 05:46:50,414 INFO L226 Difference]: Without dead ends: 40627 [2018-11-23 05:46:50,415 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:50,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40627 states. [2018-11-23 05:46:51,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40627 to 23661. [2018-11-23 05:46:51,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23661 states. [2018-11-23 05:46:51,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23661 states to 23661 states and 92542 transitions. [2018-11-23 05:46:51,455 INFO L78 Accepts]: Start accepts. Automaton has 23661 states and 92542 transitions. Word has length 36 [2018-11-23 05:46:51,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:51,456 INFO L480 AbstractCegarLoop]: Abstraction has 23661 states and 92542 transitions. [2018-11-23 05:46:51,456 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 05:46:51,456 INFO L276 IsEmpty]: Start isEmpty. Operand 23661 states and 92542 transitions. [2018-11-23 05:46:51,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-11-23 05:46:51,461 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:51,462 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:51,462 INFO L423 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:51,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:51,462 INFO L82 PathProgramCache]: Analyzing trace with hash -1826409231, now seen corresponding path program 1 times [2018-11-23 05:46:51,462 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:51,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:51,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:51,466 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:51,466 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:51,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:51,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:51,547 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:51,547 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:46:51,547 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:51,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:46:51,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:46:51,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:51,551 INFO L87 Difference]: Start difference. First operand 23661 states and 92542 transitions. Second operand 5 states. [2018-11-23 05:46:52,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:52,253 INFO L93 Difference]: Finished difference Result 64829 states and 241368 transitions. [2018-11-23 05:46:52,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:52,253 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 43 [2018-11-23 05:46:52,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:52,417 INFO L225 Difference]: With dead ends: 64829 [2018-11-23 05:46:52,417 INFO L226 Difference]: Without dead ends: 64669 [2018-11-23 05:46:52,418 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:52,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64669 states. [2018-11-23 05:46:53,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64669 to 37141. [2018-11-23 05:46:53,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37141 states. [2018-11-23 05:46:53,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37141 states to 37141 states and 138283 transitions. [2018-11-23 05:46:53,388 INFO L78 Accepts]: Start accepts. Automaton has 37141 states and 138283 transitions. Word has length 43 [2018-11-23 05:46:53,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:53,389 INFO L480 AbstractCegarLoop]: Abstraction has 37141 states and 138283 transitions. [2018-11-23 05:46:53,389 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:46:53,389 INFO L276 IsEmpty]: Start isEmpty. Operand 37141 states and 138283 transitions. [2018-11-23 05:46:53,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-11-23 05:46:53,392 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:53,392 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:53,393 INFO L423 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:53,393 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:53,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1003362560, now seen corresponding path program 1 times [2018-11-23 05:46:53,393 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:53,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:53,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:53,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:53,395 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:53,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:53,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:53,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:53,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 05:46:53,445 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:53,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 05:46:53,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 05:46:53,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:53,446 INFO L87 Difference]: Start difference. First operand 37141 states and 138283 transitions. Second operand 4 states. [2018-11-23 05:46:53,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:53,504 INFO L93 Difference]: Finished difference Result 12363 states and 41176 transitions. [2018-11-23 05:46:53,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 05:46:53,504 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 44 [2018-11-23 05:46:53,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:53,527 INFO L225 Difference]: With dead ends: 12363 [2018-11-23 05:46:53,527 INFO L226 Difference]: Without dead ends: 11842 [2018-11-23 05:46:53,528 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:53,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11842 states. [2018-11-23 05:46:53,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11842 to 11842. [2018-11-23 05:46:53,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11842 states. [2018-11-23 05:46:53,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11842 states to 11842 states and 39621 transitions. [2018-11-23 05:46:53,707 INFO L78 Accepts]: Start accepts. Automaton has 11842 states and 39621 transitions. Word has length 44 [2018-11-23 05:46:53,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:53,707 INFO L480 AbstractCegarLoop]: Abstraction has 11842 states and 39621 transitions. [2018-11-23 05:46:53,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 05:46:53,707 INFO L276 IsEmpty]: Start isEmpty. Operand 11842 states and 39621 transitions. [2018-11-23 05:46:53,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 05:46:53,711 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:53,711 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:53,711 INFO L423 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:53,711 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:53,711 INFO L82 PathProgramCache]: Analyzing trace with hash 77217480, now seen corresponding path program 1 times [2018-11-23 05:46:53,711 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:53,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:53,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:53,714 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:53,714 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:53,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:53,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:53,777 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:53,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 05:46:53,777 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:53,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 05:46:53,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 05:46:53,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:53,778 INFO L87 Difference]: Start difference. First operand 11842 states and 39621 transitions. Second operand 4 states. [2018-11-23 05:46:53,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:53,972 INFO L93 Difference]: Finished difference Result 17018 states and 55692 transitions. [2018-11-23 05:46:53,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 05:46:53,973 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 57 [2018-11-23 05:46:53,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:54,003 INFO L225 Difference]: With dead ends: 17018 [2018-11-23 05:46:54,003 INFO L226 Difference]: Without dead ends: 17018 [2018-11-23 05:46:54,003 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:54,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17018 states. [2018-11-23 05:46:54,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17018 to 12878. [2018-11-23 05:46:54,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12878 states. [2018-11-23 05:46:54,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12878 states to 12878 states and 42719 transitions. [2018-11-23 05:46:54,206 INFO L78 Accepts]: Start accepts. Automaton has 12878 states and 42719 transitions. Word has length 57 [2018-11-23 05:46:54,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:54,207 INFO L480 AbstractCegarLoop]: Abstraction has 12878 states and 42719 transitions. [2018-11-23 05:46:54,207 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 05:46:54,207 INFO L276 IsEmpty]: Start isEmpty. Operand 12878 states and 42719 transitions. [2018-11-23 05:46:54,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-11-23 05:46:54,212 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:54,212 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:54,213 INFO L423 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:54,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:54,213 INFO L82 PathProgramCache]: Analyzing trace with hash -257181528, now seen corresponding path program 1 times [2018-11-23 05:46:54,213 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:54,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,215 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:54,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,215 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:54,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:54,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:54,268 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:54,268 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:46:54,268 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:54,268 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:46:54,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:46:54,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:54,269 INFO L87 Difference]: Start difference. First operand 12878 states and 42719 transitions. Second operand 5 states. [2018-11-23 05:46:54,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:54,312 INFO L93 Difference]: Finished difference Result 2522 states and 6736 transitions. [2018-11-23 05:46:54,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:46:54,313 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-11-23 05:46:54,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:54,316 INFO L225 Difference]: With dead ends: 2522 [2018-11-23 05:46:54,317 INFO L226 Difference]: Without dead ends: 2110 [2018-11-23 05:46:54,317 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:54,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2110 states. [2018-11-23 05:46:54,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2110 to 2007. [2018-11-23 05:46:54,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2007 states. [2018-11-23 05:46:54,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2007 states to 2007 states and 5339 transitions. [2018-11-23 05:46:54,426 INFO L78 Accepts]: Start accepts. Automaton has 2007 states and 5339 transitions. Word has length 57 [2018-11-23 05:46:54,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:54,426 INFO L480 AbstractCegarLoop]: Abstraction has 2007 states and 5339 transitions. [2018-11-23 05:46:54,426 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:46:54,426 INFO L276 IsEmpty]: Start isEmpty. Operand 2007 states and 5339 transitions. [2018-11-23 05:46:54,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-23 05:46:54,429 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:54,429 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:54,430 INFO L423 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:54,430 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:54,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1812807878, now seen corresponding path program 1 times [2018-11-23 05:46:54,430 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:54,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:54,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,431 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:54,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:54,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:54,523 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:54,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 05:46:54,523 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:54,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:46:54,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:46:54,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:54,524 INFO L87 Difference]: Start difference. First operand 2007 states and 5339 transitions. Second operand 7 states. [2018-11-23 05:46:54,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:54,767 INFO L93 Difference]: Finished difference Result 2413 states and 6166 transitions. [2018-11-23 05:46:54,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:54,767 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 90 [2018-11-23 05:46:54,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:54,769 INFO L225 Difference]: With dead ends: 2413 [2018-11-23 05:46:54,769 INFO L226 Difference]: Without dead ends: 2329 [2018-11-23 05:46:54,770 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=32, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:54,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2329 states. [2018-11-23 05:46:54,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2329 to 2253. [2018-11-23 05:46:54,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2253 states. [2018-11-23 05:46:54,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2253 states to 2253 states and 5861 transitions. [2018-11-23 05:46:54,785 INFO L78 Accepts]: Start accepts. Automaton has 2253 states and 5861 transitions. Word has length 90 [2018-11-23 05:46:54,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:54,786 INFO L480 AbstractCegarLoop]: Abstraction has 2253 states and 5861 transitions. [2018-11-23 05:46:54,786 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:46:54,786 INFO L276 IsEmpty]: Start isEmpty. Operand 2253 states and 5861 transitions. [2018-11-23 05:46:54,788 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-23 05:46:54,788 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:54,788 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:54,788 INFO L423 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:54,788 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:54,788 INFO L82 PathProgramCache]: Analyzing trace with hash -843226855, now seen corresponding path program 1 times [2018-11-23 05:46:54,788 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:54,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:54,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:54,790 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:54,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:54,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:54,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:54,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:46:54,854 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:54,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:46:54,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:46:54,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:54,855 INFO L87 Difference]: Start difference. First operand 2253 states and 5861 transitions. Second operand 5 states. [2018-11-23 05:46:54,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:54,987 INFO L93 Difference]: Finished difference Result 2790 states and 7091 transitions. [2018-11-23 05:46:54,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:54,988 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-11-23 05:46:54,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:54,992 INFO L225 Difference]: With dead ends: 2790 [2018-11-23 05:46:54,992 INFO L226 Difference]: Without dead ends: 2751 [2018-11-23 05:46:54,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:54,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2751 states. [2018-11-23 05:46:55,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2751 to 2379. [2018-11-23 05:46:55,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2379 states. [2018-11-23 05:46:55,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2379 states to 2379 states and 6127 transitions. [2018-11-23 05:46:55,017 INFO L78 Accepts]: Start accepts. Automaton has 2379 states and 6127 transitions. Word has length 90 [2018-11-23 05:46:55,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:55,017 INFO L480 AbstractCegarLoop]: Abstraction has 2379 states and 6127 transitions. [2018-11-23 05:46:55,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:46:55,017 INFO L276 IsEmpty]: Start isEmpty. Operand 2379 states and 6127 transitions. [2018-11-23 05:46:55,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-23 05:46:55,019 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:55,020 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:55,020 INFO L423 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:55,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:55,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1989063700, now seen corresponding path program 1 times [2018-11-23 05:46:55,020 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:55,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:55,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,022 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:55,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:55,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:55,052 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:55,052 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 05:46:55,052 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:55,052 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 05:46:55,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 05:46:55,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:46:55,053 INFO L87 Difference]: Start difference. First operand 2379 states and 6127 transitions. Second operand 3 states. [2018-11-23 05:46:55,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:55,140 INFO L93 Difference]: Finished difference Result 2489 states and 6361 transitions. [2018-11-23 05:46:55,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 05:46:55,140 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 90 [2018-11-23 05:46:55,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:55,143 INFO L225 Difference]: With dead ends: 2489 [2018-11-23 05:46:55,143 INFO L226 Difference]: Without dead ends: 2489 [2018-11-23 05:46:55,143 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:46:55,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2489 states. [2018-11-23 05:46:55,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2489 to 2417. [2018-11-23 05:46:55,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2417 states. [2018-11-23 05:46:55,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2417 states to 2417 states and 6205 transitions. [2018-11-23 05:46:55,162 INFO L78 Accepts]: Start accepts. Automaton has 2417 states and 6205 transitions. Word has length 90 [2018-11-23 05:46:55,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:55,163 INFO L480 AbstractCegarLoop]: Abstraction has 2417 states and 6205 transitions. [2018-11-23 05:46:55,163 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 05:46:55,163 INFO L276 IsEmpty]: Start isEmpty. Operand 2417 states and 6205 transitions. [2018-11-23 05:46:55,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:55,165 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:55,165 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:55,165 INFO L423 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:55,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:55,166 INFO L82 PathProgramCache]: Analyzing trace with hash 353378826, now seen corresponding path program 1 times [2018-11-23 05:46:55,166 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:55,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:55,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,167 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:55,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:55,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:55,203 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:55,203 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 05:46:55,203 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:55,204 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 05:46:55,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 05:46:55,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:55,204 INFO L87 Difference]: Start difference. First operand 2417 states and 6205 transitions. Second operand 4 states. [2018-11-23 05:46:55,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:55,332 INFO L93 Difference]: Finished difference Result 4371 states and 11304 transitions. [2018-11-23 05:46:55,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 05:46:55,332 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-23 05:46:55,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:55,336 INFO L225 Difference]: With dead ends: 4371 [2018-11-23 05:46:55,336 INFO L226 Difference]: Without dead ends: 4371 [2018-11-23 05:46:55,336 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:55,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4371 states. [2018-11-23 05:46:55,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4371 to 2349. [2018-11-23 05:46:55,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2349 states. [2018-11-23 05:46:55,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2349 states to 2349 states and 5959 transitions. [2018-11-23 05:46:55,361 INFO L78 Accepts]: Start accepts. Automaton has 2349 states and 5959 transitions. Word has length 92 [2018-11-23 05:46:55,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:55,362 INFO L480 AbstractCegarLoop]: Abstraction has 2349 states and 5959 transitions. [2018-11-23 05:46:55,362 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 05:46:55,362 INFO L276 IsEmpty]: Start isEmpty. Operand 2349 states and 5959 transitions. [2018-11-23 05:46:55,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:55,364 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:55,364 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:55,364 INFO L423 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:55,365 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:55,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1349001223, now seen corresponding path program 1 times [2018-11-23 05:46:55,365 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:55,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:55,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,366 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:55,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:55,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:55,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:55,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-11-23 05:46:55,429 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:55,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 05:46:55,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 05:46:55,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:55,430 INFO L87 Difference]: Start difference. First operand 2349 states and 5959 transitions. Second operand 4 states. [2018-11-23 05:46:55,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:55,512 INFO L93 Difference]: Finished difference Result 2685 states and 6879 transitions. [2018-11-23 05:46:55,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 05:46:55,513 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 92 [2018-11-23 05:46:55,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:55,516 INFO L225 Difference]: With dead ends: 2685 [2018-11-23 05:46:55,516 INFO L226 Difference]: Without dead ends: 2685 [2018-11-23 05:46:55,516 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 05:46:55,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2685 states. [2018-11-23 05:46:55,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2685 to 2653. [2018-11-23 05:46:55,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2653 states. [2018-11-23 05:46:55,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2653 states to 2653 states and 6799 transitions. [2018-11-23 05:46:55,545 INFO L78 Accepts]: Start accepts. Automaton has 2653 states and 6799 transitions. Word has length 92 [2018-11-23 05:46:55,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:55,547 INFO L480 AbstractCegarLoop]: Abstraction has 2653 states and 6799 transitions. [2018-11-23 05:46:55,547 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 05:46:55,547 INFO L276 IsEmpty]: Start isEmpty. Operand 2653 states and 6799 transitions. [2018-11-23 05:46:55,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:55,550 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:55,551 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:55,551 INFO L423 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:55,551 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:55,551 INFO L82 PathProgramCache]: Analyzing trace with hash 868756730, now seen corresponding path program 1 times [2018-11-23 05:46:55,551 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:55,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:55,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,553 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:55,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:55,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:55,643 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:55,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:55,644 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:55,644 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:55,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:55,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:55,644 INFO L87 Difference]: Start difference. First operand 2653 states and 6799 transitions. Second operand 6 states. [2018-11-23 05:46:55,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:55,867 INFO L93 Difference]: Finished difference Result 3995 states and 10189 transitions. [2018-11-23 05:46:55,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:46:55,868 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-23 05:46:55,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:55,872 INFO L225 Difference]: With dead ends: 3995 [2018-11-23 05:46:55,872 INFO L226 Difference]: Without dead ends: 3963 [2018-11-23 05:46:55,873 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:55,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3963 states. [2018-11-23 05:46:55,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3963 to 3559. [2018-11-23 05:46:55,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3559 states. [2018-11-23 05:46:55,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3559 states to 3559 states and 9122 transitions. [2018-11-23 05:46:55,918 INFO L78 Accepts]: Start accepts. Automaton has 3559 states and 9122 transitions. Word has length 92 [2018-11-23 05:46:55,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:55,918 INFO L480 AbstractCegarLoop]: Abstraction has 3559 states and 9122 transitions. [2018-11-23 05:46:55,918 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:55,919 INFO L276 IsEmpty]: Start isEmpty. Operand 3559 states and 9122 transitions. [2018-11-23 05:46:55,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:55,923 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:55,923 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:55,924 INFO L423 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:55,924 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:55,924 INFO L82 PathProgramCache]: Analyzing trace with hash 1830370747, now seen corresponding path program 1 times [2018-11-23 05:46:55,924 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:55,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:55,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:55,926 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:55,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:55,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:55,997 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:55,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 05:46:55,997 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:55,998 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:46:55,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:46:55,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:55,999 INFO L87 Difference]: Start difference. First operand 3559 states and 9122 transitions. Second operand 7 states. [2018-11-23 05:46:56,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:56,256 INFO L93 Difference]: Finished difference Result 7660 states and 19944 transitions. [2018-11-23 05:46:56,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 05:46:56,256 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 92 [2018-11-23 05:46:56,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:56,262 INFO L225 Difference]: With dead ends: 7660 [2018-11-23 05:46:56,262 INFO L226 Difference]: Without dead ends: 7660 [2018-11-23 05:46:56,262 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:46:56,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7660 states. [2018-11-23 05:46:56,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7660 to 4179. [2018-11-23 05:46:56,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4179 states. [2018-11-23 05:46:56,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4179 states to 4179 states and 10752 transitions. [2018-11-23 05:46:56,304 INFO L78 Accepts]: Start accepts. Automaton has 4179 states and 10752 transitions. Word has length 92 [2018-11-23 05:46:56,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:56,304 INFO L480 AbstractCegarLoop]: Abstraction has 4179 states and 10752 transitions. [2018-11-23 05:46:56,305 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:46:56,305 INFO L276 IsEmpty]: Start isEmpty. Operand 4179 states and 10752 transitions. [2018-11-23 05:46:56,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:56,308 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:56,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:56,309 INFO L423 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:56,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:56,309 INFO L82 PathProgramCache]: Analyzing trace with hash -1219832068, now seen corresponding path program 1 times [2018-11-23 05:46:56,309 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:56,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:56,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:56,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:56,311 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:56,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:56,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:56,408 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:56,408 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 05:46:56,408 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:56,409 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:46:56,409 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:46:56,409 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:56,409 INFO L87 Difference]: Start difference. First operand 4179 states and 10752 transitions. Second operand 7 states. [2018-11-23 05:46:56,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:56,598 INFO L93 Difference]: Finished difference Result 3925 states and 10102 transitions. [2018-11-23 05:46:56,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:56,598 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 92 [2018-11-23 05:46:56,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:56,601 INFO L225 Difference]: With dead ends: 3925 [2018-11-23 05:46:56,601 INFO L226 Difference]: Without dead ends: 3925 [2018-11-23 05:46:56,602 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:56,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3925 states. [2018-11-23 05:46:56,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3925 to 3771. [2018-11-23 05:46:56,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3771 states. [2018-11-23 05:46:56,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 9774 transitions. [2018-11-23 05:46:56,637 INFO L78 Accepts]: Start accepts. Automaton has 3771 states and 9774 transitions. Word has length 92 [2018-11-23 05:46:56,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:56,638 INFO L480 AbstractCegarLoop]: Abstraction has 3771 states and 9774 transitions. [2018-11-23 05:46:56,638 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:46:56,638 INFO L276 IsEmpty]: Start isEmpty. Operand 3771 states and 9774 transitions. [2018-11-23 05:46:56,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:56,732 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:56,732 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:56,732 INFO L423 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:56,733 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:56,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1611236628, now seen corresponding path program 1 times [2018-11-23 05:46:56,733 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:56,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:56,734 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:56,734 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:56,734 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:56,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:56,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:56,848 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:56,848 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 05:46:56,848 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:56,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:46:56,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:46:56,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:56,849 INFO L87 Difference]: Start difference. First operand 3771 states and 9774 transitions. Second operand 7 states. [2018-11-23 05:46:57,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:57,367 INFO L93 Difference]: Finished difference Result 4019 states and 10380 transitions. [2018-11-23 05:46:57,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:46:57,368 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 92 [2018-11-23 05:46:57,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:57,371 INFO L225 Difference]: With dead ends: 4019 [2018-11-23 05:46:57,371 INFO L226 Difference]: Without dead ends: 4019 [2018-11-23 05:46:57,371 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:57,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4019 states. [2018-11-23 05:46:57,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4019 to 3753. [2018-11-23 05:46:57,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3753 states. [2018-11-23 05:46:57,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3753 states to 3753 states and 9738 transitions. [2018-11-23 05:46:57,398 INFO L78 Accepts]: Start accepts. Automaton has 3753 states and 9738 transitions. Word has length 92 [2018-11-23 05:46:57,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:57,398 INFO L480 AbstractCegarLoop]: Abstraction has 3753 states and 9738 transitions. [2018-11-23 05:46:57,398 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:46:57,398 INFO L276 IsEmpty]: Start isEmpty. Operand 3753 states and 9738 transitions. [2018-11-23 05:46:57,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:57,401 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:57,401 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:57,401 INFO L423 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:57,402 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:57,402 INFO L82 PathProgramCache]: Analyzing trace with hash -200357108, now seen corresponding path program 1 times [2018-11-23 05:46:57,402 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:57,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,403 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:57,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,403 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:57,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:57,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:57,543 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:57,543 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:46:57,543 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:57,543 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:46:57,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:46:57,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:57,543 INFO L87 Difference]: Start difference. First operand 3753 states and 9738 transitions. Second operand 5 states. [2018-11-23 05:46:57,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:57,614 INFO L93 Difference]: Finished difference Result 3485 states and 9046 transitions. [2018-11-23 05:46:57,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 05:46:57,614 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 92 [2018-11-23 05:46:57,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:57,616 INFO L225 Difference]: With dead ends: 3485 [2018-11-23 05:46:57,616 INFO L226 Difference]: Without dead ends: 3485 [2018-11-23 05:46:57,617 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:57,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3485 states. [2018-11-23 05:46:57,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3485 to 3485. [2018-11-23 05:46:57,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3485 states. [2018-11-23 05:46:57,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3485 states to 3485 states and 9046 transitions. [2018-11-23 05:46:57,647 INFO L78 Accepts]: Start accepts. Automaton has 3485 states and 9046 transitions. Word has length 92 [2018-11-23 05:46:57,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:57,647 INFO L480 AbstractCegarLoop]: Abstraction has 3485 states and 9046 transitions. [2018-11-23 05:46:57,647 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:46:57,647 INFO L276 IsEmpty]: Start isEmpty. Operand 3485 states and 9046 transitions. [2018-11-23 05:46:57,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-11-23 05:46:57,652 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:57,652 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:57,652 INFO L423 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:57,652 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:57,652 INFO L82 PathProgramCache]: Analyzing trace with hash -649053747, now seen corresponding path program 1 times [2018-11-23 05:46:57,653 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:57,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,654 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:57,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,654 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:57,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:57,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:57,763 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:57,763 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:57,763 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:57,763 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:57,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:57,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:57,764 INFO L87 Difference]: Start difference. First operand 3485 states and 9046 transitions. Second operand 6 states. [2018-11-23 05:46:57,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:57,852 INFO L93 Difference]: Finished difference Result 2877 states and 7206 transitions. [2018-11-23 05:46:57,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:46:57,852 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 92 [2018-11-23 05:46:57,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:57,854 INFO L225 Difference]: With dead ends: 2877 [2018-11-23 05:46:57,854 INFO L226 Difference]: Without dead ends: 2877 [2018-11-23 05:46:57,854 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:57,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2877 states. [2018-11-23 05:46:57,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2877 to 1898. [2018-11-23 05:46:57,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1898 states. [2018-11-23 05:46:57,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1898 states to 1898 states and 4870 transitions. [2018-11-23 05:46:57,869 INFO L78 Accepts]: Start accepts. Automaton has 1898 states and 4870 transitions. Word has length 92 [2018-11-23 05:46:57,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:57,869 INFO L480 AbstractCegarLoop]: Abstraction has 1898 states and 4870 transitions. [2018-11-23 05:46:57,869 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:57,869 INFO L276 IsEmpty]: Start isEmpty. Operand 1898 states and 4870 transitions. [2018-11-23 05:46:57,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:57,871 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:57,871 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:57,871 INFO L423 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:57,871 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:57,871 INFO L82 PathProgramCache]: Analyzing trace with hash 1039708687, now seen corresponding path program 1 times [2018-11-23 05:46:57,871 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:57,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:57,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:57,873 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:57,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:57,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:57,962 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:57,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-11-23 05:46:57,962 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:57,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:46:57,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:46:57,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:57,963 INFO L87 Difference]: Start difference. First operand 1898 states and 4870 transitions. Second operand 7 states. [2018-11-23 05:46:58,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:58,255 INFO L93 Difference]: Finished difference Result 2829 states and 7095 transitions. [2018-11-23 05:46:58,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:46:58,256 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 94 [2018-11-23 05:46:58,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:58,258 INFO L225 Difference]: With dead ends: 2829 [2018-11-23 05:46:58,258 INFO L226 Difference]: Without dead ends: 2829 [2018-11-23 05:46:58,258 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:46:58,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2829 states. [2018-11-23 05:46:58,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2829 to 2248. [2018-11-23 05:46:58,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2248 states. [2018-11-23 05:46:58,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2248 states to 2248 states and 5728 transitions. [2018-11-23 05:46:58,277 INFO L78 Accepts]: Start accepts. Automaton has 2248 states and 5728 transitions. Word has length 94 [2018-11-23 05:46:58,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:58,277 INFO L480 AbstractCegarLoop]: Abstraction has 2248 states and 5728 transitions. [2018-11-23 05:46:58,277 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:46:58,277 INFO L276 IsEmpty]: Start isEmpty. Operand 2248 states and 5728 transitions. [2018-11-23 05:46:58,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:58,279 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:58,279 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:58,280 INFO L423 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:58,280 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:58,280 INFO L82 PathProgramCache]: Analyzing trace with hash -2010494128, now seen corresponding path program 1 times [2018-11-23 05:46:58,280 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:58,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:58,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,281 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:58,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:58,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:58,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:58,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:58,331 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:58,332 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:58,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:58,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:58,332 INFO L87 Difference]: Start difference. First operand 2248 states and 5728 transitions. Second operand 6 states. [2018-11-23 05:46:58,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:58,441 INFO L93 Difference]: Finished difference Result 2288 states and 5773 transitions. [2018-11-23 05:46:58,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:46:58,442 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 05:46:58,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:58,444 INFO L225 Difference]: With dead ends: 2288 [2018-11-23 05:46:58,444 INFO L226 Difference]: Without dead ends: 2288 [2018-11-23 05:46:58,444 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:46:58,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2288 states. [2018-11-23 05:46:58,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2288 to 2233. [2018-11-23 05:46:58,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2233 states. [2018-11-23 05:46:58,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2233 states to 2233 states and 5666 transitions. [2018-11-23 05:46:58,460 INFO L78 Accepts]: Start accepts. Automaton has 2233 states and 5666 transitions. Word has length 94 [2018-11-23 05:46:58,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:58,461 INFO L480 AbstractCegarLoop]: Abstraction has 2233 states and 5666 transitions. [2018-11-23 05:46:58,461 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:58,461 INFO L276 IsEmpty]: Start isEmpty. Operand 2233 states and 5666 transitions. [2018-11-23 05:46:58,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:58,463 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:58,463 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:58,463 INFO L423 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:58,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:58,463 INFO L82 PathProgramCache]: Analyzing trace with hash 1369474448, now seen corresponding path program 1 times [2018-11-23 05:46:58,463 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:58,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:58,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,465 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:58,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:58,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:58,568 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:58,569 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:58,569 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:58,569 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:58,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:58,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:58,569 INFO L87 Difference]: Start difference. First operand 2233 states and 5666 transitions. Second operand 6 states. [2018-11-23 05:46:58,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:58,762 INFO L93 Difference]: Finished difference Result 2807 states and 6976 transitions. [2018-11-23 05:46:58,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:58,763 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 05:46:58,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:58,765 INFO L225 Difference]: With dead ends: 2807 [2018-11-23 05:46:58,765 INFO L226 Difference]: Without dead ends: 2807 [2018-11-23 05:46:58,766 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:46:58,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2807 states. [2018-11-23 05:46:58,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2807 to 2281. [2018-11-23 05:46:58,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2281 states. [2018-11-23 05:46:58,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2281 states to 2281 states and 5746 transitions. [2018-11-23 05:46:58,783 INFO L78 Accepts]: Start accepts. Automaton has 2281 states and 5746 transitions. Word has length 94 [2018-11-23 05:46:58,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:58,783 INFO L480 AbstractCegarLoop]: Abstraction has 2281 states and 5746 transitions. [2018-11-23 05:46:58,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:58,783 INFO L276 IsEmpty]: Start isEmpty. Operand 2281 states and 5746 transitions. [2018-11-23 05:46:58,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:58,784 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:58,785 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:58,785 INFO L423 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:58,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:58,785 INFO L82 PathProgramCache]: Analyzing trace with hash 2138644463, now seen corresponding path program 1 times [2018-11-23 05:46:58,785 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:58,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:58,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:58,786 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:58,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:58,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:58,850 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:58,850 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 05:46:58,850 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:58,851 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:46:58,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:46:58,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:46:58,851 INFO L87 Difference]: Start difference. First operand 2281 states and 5746 transitions. Second operand 5 states. [2018-11-23 05:46:58,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:58,988 INFO L93 Difference]: Finished difference Result 2601 states and 6546 transitions. [2018-11-23 05:46:58,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:46:58,989 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 94 [2018-11-23 05:46:58,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:58,991 INFO L225 Difference]: With dead ends: 2601 [2018-11-23 05:46:58,991 INFO L226 Difference]: Without dead ends: 2601 [2018-11-23 05:46:58,992 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:58,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2601 states. [2018-11-23 05:46:59,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2601 to 2009. [2018-11-23 05:46:59,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2009 states. [2018-11-23 05:46:59,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2009 states to 2009 states and 5085 transitions. [2018-11-23 05:46:59,007 INFO L78 Accepts]: Start accepts. Automaton has 2009 states and 5085 transitions. Word has length 94 [2018-11-23 05:46:59,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:59,007 INFO L480 AbstractCegarLoop]: Abstraction has 2009 states and 5085 transitions. [2018-11-23 05:46:59,007 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:46:59,007 INFO L276 IsEmpty]: Start isEmpty. Operand 2009 states and 5085 transitions. [2018-11-23 05:46:59,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:59,009 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:59,009 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:59,009 INFO L423 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:59,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:59,010 INFO L82 PathProgramCache]: Analyzing trace with hash -911558352, now seen corresponding path program 1 times [2018-11-23 05:46:59,010 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:59,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:59,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,011 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:59,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:59,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:59,124 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:59,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-11-23 05:46:59,125 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:59,125 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 05:46:59,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 05:46:59,125 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:46:59,125 INFO L87 Difference]: Start difference. First operand 2009 states and 5085 transitions. Second operand 10 states. [2018-11-23 05:46:59,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:59,369 INFO L93 Difference]: Finished difference Result 3694 states and 9553 transitions. [2018-11-23 05:46:59,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:46:59,369 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 94 [2018-11-23 05:46:59,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:59,371 INFO L225 Difference]: With dead ends: 3694 [2018-11-23 05:46:59,371 INFO L226 Difference]: Without dead ends: 1719 [2018-11-23 05:46:59,372 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=171, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:46:59,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1719 states. [2018-11-23 05:46:59,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1719 to 1719. [2018-11-23 05:46:59,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1719 states. [2018-11-23 05:46:59,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1719 states to 1719 states and 4515 transitions. [2018-11-23 05:46:59,383 INFO L78 Accepts]: Start accepts. Automaton has 1719 states and 4515 transitions. Word has length 94 [2018-11-23 05:46:59,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:59,383 INFO L480 AbstractCegarLoop]: Abstraction has 1719 states and 4515 transitions. [2018-11-23 05:46:59,383 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 05:46:59,384 INFO L276 IsEmpty]: Start isEmpty. Operand 1719 states and 4515 transitions. [2018-11-23 05:46:59,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:59,385 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:59,386 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:59,386 INFO L423 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:59,386 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:59,386 INFO L82 PathProgramCache]: Analyzing trace with hash -350187536, now seen corresponding path program 1 times [2018-11-23 05:46:59,386 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:59,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,387 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:59,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,388 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:59,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:59,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:59,439 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:59,439 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:59,439 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:59,440 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:59,440 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:59,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:59,440 INFO L87 Difference]: Start difference. First operand 1719 states and 4515 transitions. Second operand 6 states. [2018-11-23 05:46:59,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:59,614 INFO L93 Difference]: Finished difference Result 1963 states and 5062 transitions. [2018-11-23 05:46:59,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:46:59,615 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 05:46:59,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:59,616 INFO L225 Difference]: With dead ends: 1963 [2018-11-23 05:46:59,616 INFO L226 Difference]: Without dead ends: 1963 [2018-11-23 05:46:59,617 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:46:59,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1963 states. [2018-11-23 05:46:59,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1963 to 1746. [2018-11-23 05:46:59,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1746 states. [2018-11-23 05:46:59,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1746 states to 1746 states and 4570 transitions. [2018-11-23 05:46:59,633 INFO L78 Accepts]: Start accepts. Automaton has 1746 states and 4570 transitions. Word has length 94 [2018-11-23 05:46:59,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:59,634 INFO L480 AbstractCegarLoop]: Abstraction has 1746 states and 4570 transitions. [2018-11-23 05:46:59,634 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:59,634 INFO L276 IsEmpty]: Start isEmpty. Operand 1746 states and 4570 transitions. [2018-11-23 05:46:59,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:59,635 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:59,636 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:59,636 INFO L423 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:59,636 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:59,636 INFO L82 PathProgramCache]: Analyzing trace with hash -20421775, now seen corresponding path program 1 times [2018-11-23 05:46:59,636 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:59,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,637 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:59,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,637 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:59,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:59,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:59,738 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:59,738 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:59,738 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:59,739 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:59,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:59,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:59,741 INFO L87 Difference]: Start difference. First operand 1746 states and 4570 transitions. Second operand 6 states. [2018-11-23 05:46:59,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:46:59,826 INFO L93 Difference]: Finished difference Result 1805 states and 4679 transitions. [2018-11-23 05:46:59,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:46:59,826 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 05:46:59,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:46:59,828 INFO L225 Difference]: With dead ends: 1805 [2018-11-23 05:46:59,828 INFO L226 Difference]: Without dead ends: 1789 [2018-11-23 05:46:59,829 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:46:59,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1789 states. [2018-11-23 05:46:59,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1789 to 1719. [2018-11-23 05:46:59,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1719 states. [2018-11-23 05:46:59,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1719 states to 1719 states and 4507 transitions. [2018-11-23 05:46:59,854 INFO L78 Accepts]: Start accepts. Automaton has 1719 states and 4507 transitions. Word has length 94 [2018-11-23 05:46:59,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:46:59,855 INFO L480 AbstractCegarLoop]: Abstraction has 1719 states and 4507 transitions. [2018-11-23 05:46:59,855 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:46:59,855 INFO L276 IsEmpty]: Start isEmpty. Operand 1719 states and 4507 transitions. [2018-11-23 05:46:59,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:46:59,858 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:46:59,858 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:46:59,858 INFO L423 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:46:59,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:46:59,858 INFO L82 PathProgramCache]: Analyzing trace with hash -2050928015, now seen corresponding path program 1 times [2018-11-23 05:46:59,859 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:46:59,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,860 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:46:59,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:46:59,860 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:46:59,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:46:59,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:46:59,968 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:46:59,968 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 05:46:59,968 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 05:46:59,969 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:46:59,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:46:59,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:46:59,969 INFO L87 Difference]: Start difference. First operand 1719 states and 4507 transitions. Second operand 6 states. [2018-11-23 05:47:00,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:47:00,131 INFO L93 Difference]: Finished difference Result 1761 states and 4583 transitions. [2018-11-23 05:47:00,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:47:00,131 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 94 [2018-11-23 05:47:00,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:47:00,133 INFO L225 Difference]: With dead ends: 1761 [2018-11-23 05:47:00,133 INFO L226 Difference]: Without dead ends: 1761 [2018-11-23 05:47:00,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:47:00,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1761 states. [2018-11-23 05:47:00,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1761 to 1754. [2018-11-23 05:47:00,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1754 states. [2018-11-23 05:47:00,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1754 states to 1754 states and 4570 transitions. [2018-11-23 05:47:00,150 INFO L78 Accepts]: Start accepts. Automaton has 1754 states and 4570 transitions. Word has length 94 [2018-11-23 05:47:00,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:47:00,150 INFO L480 AbstractCegarLoop]: Abstraction has 1754 states and 4570 transitions. [2018-11-23 05:47:00,150 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:47:00,150 INFO L276 IsEmpty]: Start isEmpty. Operand 1754 states and 4570 transitions. [2018-11-23 05:47:00,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 05:47:00,152 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:47:00,152 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:47:00,152 INFO L423 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:47:00,153 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:47:00,153 INFO L82 PathProgramCache]: Analyzing trace with hash -1721162254, now seen corresponding path program 2 times [2018-11-23 05:47:00,153 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 05:47:00,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:47:00,154 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:47:00,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:47:00,154 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 05:47:00,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:47:00,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:47:00,210 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [473] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [363] L-1-->L671: Formula: (= |v_#valid_5| (store |v_#valid_6| 0 0)) InVars {#valid=|v_#valid_6|} OutVars{#valid=|v_#valid_5|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [512] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [387] L673-->L674: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [487] L674-->L675: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 [435] L675-->L677: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [483] L677-->L678: Formula: (= v_~x~0_9 0) InVars {} OutVars{~x~0=v_~x~0_9} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [430] L678-->L679: Formula: (= v_~x$flush_delayed~0_4 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [523] L679-->L680: Formula: (= v_~x$mem_tmp~0_2 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [453] L680-->L681: Formula: (= v_~x$r_buff0_thd0~0_16 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_16} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [389] L681-->L682: Formula: (= v_~x$r_buff0_thd1~0_13 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [511] L682-->L683: Formula: (= v_~x$r_buff0_thd2~0_14 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [445] L683-->L684: Formula: (= v_~x$r_buff1_thd0~0_10 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_10} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [386] L684-->L685: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [486] L685-->L686: Formula: (= v_~x$r_buff1_thd2~0_9 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [434] L686-->L687: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [380] L687-->L688: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [482] L688-->L689: Formula: (= v_~x$w_buff0~0_5 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [428] L689-->L690: Formula: (= v_~x$w_buff0_used~0_38 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_38} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [522] L690-->L691: Formula: (= v_~x$w_buff1~0_4 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_4} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [451] L691-->L693: Formula: (= v_~x$w_buff1_used~0_24 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [509] L693-->L694: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [444] L694-->L695: Formula: (= v_~weak$$choice0~0_1 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_1} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [385] L695-->L-1-1: Formula: (= v_~weak$$choice2~0_7 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [510] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [506] L-1-2-->L755: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_3|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_1|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_1|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_1|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_1|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_1|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_1|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_3|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_1|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_2|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_1|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_1|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_1|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_3|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_1|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_1|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_1|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1457~0.offset, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet25.base, ULTIMATE.start_main_~#t1458~0.base, ULTIMATE.start_main_~#t1457~0.base, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~nondet26.offset, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~nondet25.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1458~0.offset, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_#t~nondet18] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [422] L755-->L755-1: Formula: (and (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1457~0.base_4| 4) |v_#length_1|) (not (= 0 |v_ULTIMATE.start_main_~#t1457~0.base_4|)) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#t1457~0.base_4| 1) |v_#valid_7|) (= 0 |v_ULTIMATE.start_main_~#t1457~0.offset_4|) (= 0 (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1457~0.base_4|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_4|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_4|, #length=|v_#length_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1457~0.offset, ULTIMATE.start_main_~#t1457~0.base, #valid, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [424] L755-1-->L756: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1457~0.base_5| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1457~0.base_5|) |v_ULTIMATE.start_main_~#t1457~0.offset_5| 0))) InVars {ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_5|, #memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_5|} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_5|, #memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [577] L756-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [516] L756-1-->L757: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [471] L757-->L757-1: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1458~0.base_4|)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1458~0.base_4| 4)) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t1458~0.base_4|)) (= 0 |v_ULTIMATE.start_main_~#t1458~0.offset_4|) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t1458~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_4|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1458~0.base, ULTIMATE.start_main_~#t1458~0.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [447] L757-1-->L758: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1458~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1458~0.base_5|) |v_ULTIMATE.start_main_~#t1458~0.offset_5| 1)) |v_#memory_int_3|) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_5|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_5|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [578] L758-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [550] P1ENTRY-->L4: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~x$w_buff0~0_2 2) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_Thread1_P1___VERIFIER_assert_~expression_1 |v_Thread1_P1___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_3 v_~x$w_buff0~0_3) (= v_~x$w_buff1_used~0_15 v_~x$w_buff0_used~0_22) (= v_~x$w_buff0_used~0_21 1) (= |v_Thread1_P1___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_21 256))) (not (= 0 (mod v_~x$w_buff1_used~0_15 256))))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_22} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~x$w_buff1~0=v_~x$w_buff1~0_3, Thread1_P1___VERIFIER_assert_#in~expression=|v_Thread1_P1___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_15, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_21} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1___VERIFIER_assert_~expression, Thread1_P1_~arg.offset, Thread1_P1_~arg.base, ~x$w_buff1~0, Thread1_P1___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [552] L4-->L4-3: Formula: (not (= v_Thread1_P1___VERIFIER_assert_~expression_3 0)) InVars {Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} OutVars{Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [555] L4-3-->L733: Formula: (and (= v_~x$r_buff1_thd2~0_8 v_~x$r_buff0_thd2~0_11) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_2) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff0_thd2~0_10 1) (= v_~x$r_buff1_thd1~0_8 v_~x$r_buff0_thd1~0_12)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_11} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 [528] P0ENTRY-->L705: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x~0_1 1) (= v_~y~0_1 1)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0_~arg.offset, Thread0_P0_~arg.base, ~y~0, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [530] L705-->L705-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd1~0_4 256)) (= 0 (mod v_~x$w_buff0_used~0_3 256))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [533] L705-2-->L705-4: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_4 256)) (= (mod v_~x$r_buff1_thd1~0_4 256) 0)) (= |v_Thread0_P0_#t~ite3_3| v_~x~0_2)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, ~x~0=v_~x~0_2} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_3|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite3] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [536] L705-4-->L705-5: Formula: (= |v_Thread0_P0_#t~ite4_4| |v_Thread0_P0_#t~ite3_4|) InVars {Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_4|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread0_P0_#t~ite4|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [531] L705-5-->L706: Formula: (= v_~x~0_3 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [535] L706-->L706-2: Formula: (and (= |v_Thread0_P0_#t~ite5_2| v_~x$w_buff0_used~0_7) (or (= 0 (mod v_~x$w_buff0_used~0_7 256)) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [537] L706-2-->L707: Formula: (= v_~x$w_buff0_used~0_8 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_8} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [539] L707-->L707-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_6) (or (= (mod v_~x$w_buff0_used~0_10 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0)) (or (= 0 (mod v_~x$w_buff1_used~0_6 256)) (= (mod v_~x$r_buff1_thd1~0_7 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [540] L707-2-->L708: Formula: (= v_~x$w_buff1_used~0_7 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 [556] L733-->L733-5: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd2~0_12 256))) (= |v_Thread1_P1_#t~ite11_1| v_~x$w_buff0~0_4) (not (= 0 (mod v_~x$w_buff0_used~0_23 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_4, Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} AuxVars[] AssignedVars[Thread1_P1_#t~ite11] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 [558] L733-5-->L734: Formula: (= v_~x~0_5 |v_Thread1_P1_#t~ite11_2|) InVars {Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_2|} OutVars{Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_3|, ~x~0=v_~x~0_5, Thread1_P1_#t~ite10=|v_Thread1_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite10, Thread1_P1_#t~ite11, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [561] L734-->L734-2: Formula: (and (not (= (mod v_~x$w_buff0_used~0_12 256) 0)) (= |v_Thread1_P1_#t~ite12_1| 0) (not (= (mod v_~x$r_buff0_thd2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} AuxVars[] AssignedVars[Thread1_P1_#t~ite12] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite12|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [564] L734-2-->L735: Formula: (= v_~x$w_buff0_used~0_14 |v_Thread1_P1_#t~ite12_3|) InVars {Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_3|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_14} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [566] L735-->L735-2: Formula: (and (= |v_Thread1_P1_#t~ite13_2| v_~x$w_buff1_used~0_11) (or (= 0 (mod v_~x$w_buff1_used~0_11 256)) (= 0 (mod v_~x$r_buff1_thd2~0_4 256))) (or (= (mod v_~x$r_buff0_thd2~0_4 256) 0) (= (mod v_~x$w_buff0_used~0_16 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [567] L735-2-->L736: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite13_3|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [569] L736-->L736-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_18 256))) (= |v_Thread1_P1_#t~ite14_2| v_~x$r_buff0_thd2~0_6)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} AuxVars[] AssignedVars[Thread1_P1_#t~ite14] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite14|=1, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [570] L736-2-->L737: Formula: (= v_~x$r_buff0_thd2~0_7 |v_Thread1_P1_#t~ite14_3|) InVars {Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite14, ~x$r_buff0_thd2~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [572] L737-->L737-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_20 256) 0) (= (mod v_~x$r_buff0_thd2~0_9 256) 0)) (= |v_Thread1_P1_#t~ite15_2| v_~x$r_buff1_thd2~0_6) (or (= 0 (mod v_~x$r_buff1_thd2~0_6 256)) (= 0 (mod v_~x$w_buff1_used~0_14 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} AuxVars[] AssignedVars[Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite15|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [573] L737-2-->L742: Formula: (and (= v_~x$r_buff1_thd2~0_7 |v_Thread1_P1_#t~ite15_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_7, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [542] L708-->L708-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_1) (or (= (mod v_~x$w_buff0_used~0_1 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_1 256)))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [543] L708-2-->L709: Formula: (= v_~x$r_buff0_thd1~0_3 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [545] L709-->L709-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_5 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_6 256))) (or (= (mod v_~x$r_buff1_thd1~0_3 256) 0) (= (mod v_~x$w_buff1_used~0_3 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_3)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [546] L709-2-->L714: Formula: (and (= v_~x$r_buff1_thd1~0_5 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [413] L758-1-->L762: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [500] L762-->L764: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [368] L764-->L764-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_40 256)) (= 0 (mod v_~x$r_buff0_thd0~0_18 256))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [377] L764-2-->L764-4: Formula: (and (or (= (mod v_~x$w_buff1_used~0_26 256) 0) (= 0 (mod v_~x$r_buff1_thd0~0_12 256))) (= |v_ULTIMATE.start_main_#t~ite19_3| v_~x~0_10)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [352] L764-4-->L764-5: Formula: (= |v_ULTIMATE.start_main_#t~ite20_3| |v_ULTIMATE.start_main_#t~ite19_4|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_3|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [354] L764-5-->L765: Formula: (= v_~x~0_11 |v_ULTIMATE.start_main_#t~ite20_5|) InVars {ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_5|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_4|, ~x~0=v_~x~0_11, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [478] L765-->L765-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_20 256)) (= (mod v_~x$w_buff0_used~0_42 256) 0)) (= |v_ULTIMATE.start_main_#t~ite21_3| v_~x$w_buff0_used~0_42)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [481] L765-2-->L766: Formula: (= v_~x$w_buff0_used~0_43 |v_ULTIMATE.start_main_#t~ite21_5|) InVars {ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_5|} OutVars{ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_43} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [421] L766-->L766-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd0~0_14 256)) (= 0 (mod v_~x$w_buff1_used~0_28 256))) (or (= (mod v_~x$w_buff0_used~0_45 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_22 256))) (= |v_ULTIMATE.start_main_#t~ite22_3| v_~x$w_buff1_used~0_28)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [427] L766-2-->L767: Formula: (= v_~x$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite22_5|) InVars {ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [362] L767-->L767-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_47 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_24 256))) (= |v_ULTIMATE.start_main_#t~ite23_3| v_~x$r_buff0_thd0~0_24)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [519] L767-2-->L768: Formula: (= v_~x$r_buff0_thd0~0_25 |v_ULTIMATE.start_main_#t~ite23_5|) InVars {ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_25, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [469] L768-->L768-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite24_3| v_~x$r_buff1_thd0~0_16) (or (= (mod v_~x$w_buff1_used~0_31 256) 0) (= (mod v_~x$r_buff1_thd0~0_16 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= (mod v_~x$r_buff0_thd0~0_27 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [450] L768-2-->L775: Formula: (and (= v_~weak$$choice2~0_8 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet26.base_3| |v_ULTIMATE.start_main_#t~nondet26.offset_3|)) 0 1)) (= v_~x$r_buff1_thd0~0_17 |v_ULTIMATE.start_main_#t~ite24_5|) (= v_~x$flush_delayed~0_5 v_~weak$$choice2~0_8) (= v_~weak$$choice0~0_2 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet25.base_3| |v_ULTIMATE.start_main_#t~nondet25.offset_3|)) 0 1)) (= v_~x$mem_tmp~0_3 v_~x~0_12)) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_5|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_3|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_3|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_3|, ~x~0=v_~x~0_12} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_5, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_4|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_3, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_2|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_17, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[~weak$$choice0~0, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet26.offset, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet25.base, ~weak$$choice2~0, ULTIMATE.start_main_#t~nondet25.offset, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [365] L775-->L775-5: Formula: (and (= |v_ULTIMATE.start_main_#t~ite28_2| v_~x~0_13) (let ((.cse0 (= (mod v_~x$r_buff0_thd0~0_28 256) 0))) (or (and (= (mod v_~x$r_buff1_thd0~0_18 256) 0) .cse0) (and (= (mod v_~x$w_buff1_used~0_32 256) 0) .cse0) (= (mod v_~x$w_buff0_used~0_50 256) 0)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [353] L775-5-->L776: Formula: (= v_~x~0_14 |v_ULTIMATE.start_main_#t~ite28_5|) InVars {ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_5|} OutVars{ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_5|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_4|, ~x~0=v_~x~0_14} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite27, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [475] L776-->L776-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite31_2| v_~x$w_buff0~0_8) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_8, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_8, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_2|, ~weak$$choice2~0=v_~weak$$choice2~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [470] L776-8-->L777: Formula: (= v_~x$w_buff0~0_12 |v_ULTIMATE.start_main_#t~ite31_5|) InVars {ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_5|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_12, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_5|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_4|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_5|} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [418] L777-->L777-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_ULTIMATE.start_main_#t~ite34_2| v_~x$w_buff1~0_7)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [411] L777-8-->L778: Formula: (= v_~x$w_buff1~0_11 |v_ULTIMATE.start_main_#t~ite34_5|) InVars {ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_5|} OutVars{ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_5|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_5|, ~x$w_buff1~0=v_~x$w_buff1~0_11, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_4|} AuxVars[] AssignedVars[~x$w_buff1~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [358] L778-->L778-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite37_4| v_~x$w_buff0_used~0_62) (not (= (mod v_~weak$$choice2~0_13 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_4|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite37] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [505] L778-8-->L779: Formula: (= v_~x$w_buff0_used~0_25 |v_ULTIMATE.start_main_#t~ite37_2|) InVars {ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_2|} OutVars{ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_1|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_1|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_25} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite37, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [466] L779-->L779-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite40_1| v_~x$w_buff1_used~0_16) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_16, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [443] L779-8-->L780: Formula: (= v_~x$w_buff1_used~0_19 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_19, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite38] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [409] L780-->L780-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite43_1| v_~x$r_buff0_thd0~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [381] L780-8-->L781: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite43_4|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [503] L781-->L781-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_ULTIMATE.start_main_#t~ite46_1| v_~x$r_buff1_thd0~0_6)) InVars {~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [499] L781-8-->L783: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite46_4|) (= v_~main$tmp_guard1~0_1 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_2) (= 2 v_~x~0_6))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~x~0=v_~x~0_6} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ~x~0=v_~x~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [404] L783-->L783-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_1| v_~x$mem_tmp~0_1) (not (= 0 (mod v_~x$flush_delayed~0_1 256)))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, ~x$flush_delayed~0=v_~x$flush_delayed~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [384] L783-2-->L786: Formula: (and (= v_~x~0_8 |v_ULTIMATE.start_main_#t~ite47_4|) (= v_~x$flush_delayed~0_3 0)) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_3, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, ULTIMATE.start_main_#t~ite47, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [364] L786-->L786-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [369] L786-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [406] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [401] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [397] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); srcloc: L757 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); srcloc: L757-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite27;havoc main_#t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite31;havoc main_#t~ite30;havoc main_#t~ite29; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite35;havoc main_#t~ite36;havoc main_#t~ite37; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite40;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite41;havoc main_#t~ite43; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite45;havoc main_#t~ite44;havoc main_#t~ite46;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); srcloc: L757 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); srcloc: L757-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite27;havoc main_#t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite31;havoc main_#t~ite30;havoc main_#t~ite29; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite35;havoc main_#t~ite36;havoc main_#t~ite37; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite40;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite41;havoc main_#t~ite43; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite45;havoc main_#t~ite44;havoc main_#t~ite46;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] -1 call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] -1 call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L734] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L771] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L772] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 assume 0 != ~weak$$choice2~0 % 256; [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 assume 0 != ~weak$$choice2~0 % 256; [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 assume 0 != ~x$flush_delayed~0 % 256; [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] -1 call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] -1 call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L734] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L771] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L772] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 assume 0 != ~weak$$choice2~0 % 256; [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 assume 0 != ~weak$$choice2~0 % 256; [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 assume 0 != ~x$flush_delayed~0 % 256; [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0, main_~#t1458~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, main_~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call main_~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, main_~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L771] -1 havoc main_#t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L772] -1 havoc main_#t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0, main_~#t1458~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, main_~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call main_~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, main_~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L771] -1 havoc main_#t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L772] -1 havoc main_#t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, ~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call ~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, ~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc #t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := #t~ite20; [L764] -1 havoc #t~ite19; [L764] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := #t~ite21; [L765] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := #t~ite22; [L766] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L767] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L768] -1 havoc #t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L771] -1 havoc #t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L772] -1 havoc #t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := #t~ite28; [L775] -1 havoc #t~ite27; [L775] -1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := #t~ite31; [L776] -1 havoc #t~ite31; [L776] -1 havoc #t~ite30; [L776] -1 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := #t~ite34; [L777] -1 havoc #t~ite33; [L777] -1 havoc #t~ite32; [L777] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := #t~ite37; [L778] -1 havoc #t~ite35; [L778] -1 havoc #t~ite36; [L778] -1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := #t~ite40; [L779] -1 havoc #t~ite40; [L779] -1 havoc #t~ite38; [L779] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L780] -1 havoc #t~ite42; [L780] -1 havoc #t~ite41; [L780] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L781] -1 havoc #t~ite45; [L781] -1 havoc #t~ite44; [L781] -1 havoc #t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := #t~ite47; [L783] -1 havoc #t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, ~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call ~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, ~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc #t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := #t~ite20; [L764] -1 havoc #t~ite19; [L764] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := #t~ite21; [L765] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := #t~ite22; [L766] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L767] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L768] -1 havoc #t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L771] -1 havoc #t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L772] -1 havoc #t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := #t~ite28; [L775] -1 havoc #t~ite27; [L775] -1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := #t~ite31; [L776] -1 havoc #t~ite31; [L776] -1 havoc #t~ite30; [L776] -1 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := #t~ite34; [L777] -1 havoc #t~ite33; [L777] -1 havoc #t~ite32; [L777] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := #t~ite37; [L778] -1 havoc #t~ite35; [L778] -1 havoc #t~ite36; [L778] -1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := #t~ite40; [L779] -1 havoc #t~ite40; [L779] -1 havoc #t~ite38; [L779] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L780] -1 havoc #t~ite42; [L780] -1 havoc #t~ite41; [L780] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L781] -1 havoc #t~ite45; [L781] -1 havoc #t~ite44; [L781] -1 havoc #t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := #t~ite47; [L783] -1 havoc #t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L674] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0] [L675] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L677] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L678] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L679] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L680] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L681] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L682] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L683] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L684] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L685] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L686] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L687] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L688] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L689] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L690] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L691] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L693] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L694] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L695] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t1457; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t1457, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L757] -1 pthread_t t1458; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L758] FCALL, FORK -1 pthread_create(&t1458, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L719] 0 x$w_buff1 = x$w_buff0 [L720] 0 x$w_buff0 = 2 [L721] 0 x$w_buff1_used = x$w_buff0_used [L722] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L724] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 0 x$r_buff0_thd2 = (_Bool)1 [L730] 0 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L699] 1 y = 1 [L702] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L706] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L707] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L735] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L736] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L736] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L737] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L737] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L740] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L709] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L709] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L712] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L760] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L765] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L767] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L768] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L771] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L772] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L773] -1 x$flush_delayed = weak$$choice2 [L774] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L776] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L777] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L778] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L778] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L779] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L779] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L780] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L781] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L781] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L782] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] -1 x = x$flush_delayed ? x$mem_tmp : x [L784] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] ----- [2018-11-23 05:47:01,972 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 05:47:01,993 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 05:47:01 BasicIcfg [2018-11-23 05:47:01,993 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 05:47:01,994 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:47:01,994 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:47:01,994 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:47:01,995 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:46:48" (3/4) ... [2018-11-23 05:47:01,997 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [473] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [363] L-1-->L671: Formula: (= |v_#valid_5| (store |v_#valid_6| 0 0)) InVars {#valid=|v_#valid_6|} OutVars{#valid=|v_#valid_5|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [512] L671-->L673: Formula: (= v_~__unbuffered_cnt~0_5 0) InVars {} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_5} AuxVars[] AssignedVars[~__unbuffered_cnt~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 [387] L673-->L674: Formula: (= v_~__unbuffered_p1_EAX~0_3 0) InVars {} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_3} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 [487] L674-->L675: Formula: (= v_~main$tmp_guard0~0_1 0) InVars {} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_1} AuxVars[] AssignedVars[~main$tmp_guard0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 [435] L675-->L677: Formula: (= v_~main$tmp_guard1~0_3 0) InVars {} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_3} AuxVars[] AssignedVars[~main$tmp_guard1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 [483] L677-->L678: Formula: (= v_~x~0_9 0) InVars {} OutVars{~x~0=v_~x~0_9} AuxVars[] AssignedVars[~x~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 [430] L678-->L679: Formula: (= v_~x$flush_delayed~0_4 0) InVars {} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_4} AuxVars[] AssignedVars[~x$flush_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 [523] L679-->L680: Formula: (= v_~x$mem_tmp~0_2 0) InVars {} OutVars{~x$mem_tmp~0=v_~x$mem_tmp~0_2} AuxVars[] AssignedVars[~x$mem_tmp~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 [453] L680-->L681: Formula: (= v_~x$r_buff0_thd0~0_16 0) InVars {} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_16} AuxVars[] AssignedVars[~x$r_buff0_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 [389] L681-->L682: Formula: (= v_~x$r_buff0_thd1~0_13 0) InVars {} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_13} AuxVars[] AssignedVars[~x$r_buff0_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 [511] L682-->L683: Formula: (= v_~x$r_buff0_thd2~0_14 0) InVars {} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_14} AuxVars[] AssignedVars[~x$r_buff0_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 [445] L683-->L684: Formula: (= v_~x$r_buff1_thd0~0_10 0) InVars {} OutVars{~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_10} AuxVars[] AssignedVars[~x$r_buff1_thd0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 [386] L684-->L685: Formula: (= v_~x$r_buff1_thd1~0_9 0) InVars {} OutVars{~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 [486] L685-->L686: Formula: (= v_~x$r_buff1_thd2~0_9 0) InVars {} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_9} AuxVars[] AssignedVars[~x$r_buff1_thd2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 [434] L686-->L687: Formula: (= v_~x$read_delayed~0_1 0) InVars {} OutVars{~x$read_delayed~0=v_~x$read_delayed~0_1} AuxVars[] AssignedVars[~x$read_delayed~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [380] L687-->L688: Formula: (and (= v_~x$read_delayed_var~0.offset_1 0) (= v_~x$read_delayed_var~0.base_1 0)) InVars {} OutVars{~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_1, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_1} AuxVars[] AssignedVars[~x$read_delayed_var~0.offset, ~x$read_delayed_var~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 [482] L688-->L689: Formula: (= v_~x$w_buff0~0_5 0) InVars {} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_5} AuxVars[] AssignedVars[~x$w_buff0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [428] L689-->L690: Formula: (= v_~x$w_buff0_used~0_38 0) InVars {} OutVars{~x$w_buff0_used~0=v_~x$w_buff0_used~0_38} AuxVars[] AssignedVars[~x$w_buff0_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 [522] L690-->L691: Formula: (= v_~x$w_buff1~0_4 0) InVars {} OutVars{~x$w_buff1~0=v_~x$w_buff1~0_4} AuxVars[] AssignedVars[~x$w_buff1~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [451] L691-->L693: Formula: (= v_~x$w_buff1_used~0_24 0) InVars {} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_24} AuxVars[] AssignedVars[~x$w_buff1_used~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 [509] L693-->L694: Formula: (= v_~y~0_3 0) InVars {} OutVars{~y~0=v_~y~0_3} AuxVars[] AssignedVars[~y~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [444] L694-->L695: Formula: (= v_~weak$$choice0~0_1 0) InVars {} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_1} AuxVars[] AssignedVars[~weak$$choice0~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [385] L695-->L-1-1: Formula: (= v_~weak$$choice2~0_7 0) InVars {} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_7} AuxVars[] AssignedVars[~weak$$choice2~0] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [510] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [506] L-1-2-->L755: Formula: true InVars {} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_3|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_1|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_1|, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_1|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_5|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_5|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_1|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_1|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_5|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_1|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_5|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_1|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_5|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_1|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_5|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_1|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_1|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_1|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_3|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_5|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_1|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_2|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_1|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_5|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_1|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_1|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_1|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_3|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_1|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_1|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_5|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_5|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_1|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1457~0.offset, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet25.base, ULTIMATE.start_main_~#t1458~0.base, ULTIMATE.start_main_~#t1457~0.base, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~nondet26.offset, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~nondet25.offset, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1458~0.offset, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_#t~nondet18] VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [422] L755-->L755-1: Formula: (and (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1457~0.base_4| 4) |v_#length_1|) (not (= 0 |v_ULTIMATE.start_main_~#t1457~0.base_4|)) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#t1457~0.base_4| 1) |v_#valid_7|) (= 0 |v_ULTIMATE.start_main_~#t1457~0.offset_4|) (= 0 (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1457~0.base_4|))) InVars {#length=|v_#length_2|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_4|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_4|, #length=|v_#length_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1457~0.offset, ULTIMATE.start_main_~#t1457~0.base, #valid, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [424] L755-1-->L756: Formula: (= |v_#memory_int_1| (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1457~0.base_5| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1457~0.base_5|) |v_ULTIMATE.start_main_~#t1457~0.offset_5| 0))) InVars {ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_5|, #memory_int=|v_#memory_int_2|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_5|} OutVars{ULTIMATE.start_main_~#t1457~0.offset=|v_ULTIMATE.start_main_~#t1457~0.offset_5|, #memory_int=|v_#memory_int_1|, ULTIMATE.start_main_~#t1457~0.base=|v_ULTIMATE.start_main_~#t1457~0.base_5|} AuxVars[] AssignedVars[#memory_int] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [577] L756-->P0ENTRY: Formula: (and (= 0 |v_Thread0_P0_#in~arg.offset_3|) (= 0 v_Thread0_P0_thidvar0_2) (= 0 |v_Thread0_P0_#in~arg.base_3|)) InVars {} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_3|, Thread0_P0_thidvar0=v_Thread0_P0_thidvar0_2, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_P0_#in~arg.base, Thread0_P0_thidvar0, Thread0_P0_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [516] L756-1-->L757: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [471] L757-->L757-1: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1458~0.base_4|)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1458~0.base_4| 4)) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_main_~#t1458~0.base_4|)) (= 0 |v_ULTIMATE.start_main_~#t1458~0.offset_4|) (= |v_#valid_9| (store |v_#valid_10| |v_ULTIMATE.start_main_~#t1458~0.base_4| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_3|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_4|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1458~0.base, ULTIMATE.start_main_~#t1458~0.offset] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 [447] L757-1-->L758: Formula: (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1458~0.base_5| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1458~0.base_5|) |v_ULTIMATE.start_main_~#t1458~0.offset_5| 1)) |v_#memory_int_3|) InVars {#memory_int=|v_#memory_int_4|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_5|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_5|} OutVars{#memory_int=|v_#memory_int_3|, ULTIMATE.start_main_~#t1458~0.base=|v_ULTIMATE.start_main_~#t1458~0.base_5|, ULTIMATE.start_main_~#t1458~0.offset=|v_ULTIMATE.start_main_~#t1458~0.offset_5|} AuxVars[] AssignedVars[#memory_int] VAL [Thread0_P0_thidvar0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 [578] L758-->P1ENTRY: Formula: (and (= 0 |v_Thread1_P1_#in~arg.base_3|) (= 0 |v_Thread1_P1_#in~arg.offset_3|) (= 1 v_Thread1_P1_thidvar0_2)) InVars {} OutVars{Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_3|, Thread1_P1_thidvar0=v_Thread1_P1_thidvar0_2, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_P1_#in~arg.base, Thread1_P1_thidvar0, Thread1_P1_#in~arg.offset] VAL [Thread0_P0_thidvar0=0, Thread1_P1_thidvar0=1, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [550] P1ENTRY-->L4: Formula: (and (= v_Thread1_P1_~arg.offset_1 |v_Thread1_P1_#in~arg.offset_1|) (= v_~x$w_buff0~0_2 2) (= v_Thread1_P1_~arg.base_1 |v_Thread1_P1_#in~arg.base_1|) (= v_Thread1_P1___VERIFIER_assert_~expression_1 |v_Thread1_P1___VERIFIER_assert_#in~expression_1|) (= v_~x$w_buff1~0_3 v_~x$w_buff0~0_3) (= v_~x$w_buff1_used~0_15 v_~x$w_buff0_used~0_22) (= v_~x$w_buff0_used~0_21 1) (= |v_Thread1_P1___VERIFIER_assert_#in~expression_1| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_21 256))) (not (= 0 (mod v_~x$w_buff1_used~0_15 256))))) 1 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_3, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_22} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_2, Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_1, Thread1_P1_#in~arg.base=|v_Thread1_P1_#in~arg.base_1|, Thread1_P1_~arg.offset=v_Thread1_P1_~arg.offset_1, Thread1_P1_~arg.base=v_Thread1_P1_~arg.base_1, ~x$w_buff1~0=v_~x$w_buff1~0_3, Thread1_P1___VERIFIER_assert_#in~expression=|v_Thread1_P1___VERIFIER_assert_#in~expression_1|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_15, Thread1_P1_#in~arg.offset=|v_Thread1_P1_#in~arg.offset_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_21} AuxVars[] AssignedVars[~x$w_buff0~0, Thread1_P1___VERIFIER_assert_~expression, Thread1_P1_~arg.offset, Thread1_P1_~arg.base, ~x$w_buff1~0, Thread1_P1___VERIFIER_assert_#in~expression, ~x$w_buff1_used~0, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [552] L4-->L4-3: Formula: (not (= v_Thread1_P1___VERIFIER_assert_~expression_3 0)) InVars {Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} OutVars{Thread1_P1___VERIFIER_assert_~expression=v_Thread1_P1___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 [555] L4-3-->L733: Formula: (and (= v_~x$r_buff1_thd2~0_8 v_~x$r_buff0_thd2~0_11) (= v_~__unbuffered_p1_EAX~0_1 v_~y~0_2) (= v_~x$r_buff1_thd0~0_1 v_~x$r_buff0_thd0~0_1) (= v_~x$r_buff0_thd2~0_10 1) (= v_~x$r_buff1_thd1~0_8 v_~x$r_buff0_thd1~0_12)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_11} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_1, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_12, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_1, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_8, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_8, ~y~0=v_~y~0_2, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_10, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_1} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 [528] P0ENTRY-->L705: Formula: (and (= v_Thread0_P0_~arg.base_1 |v_Thread0_P0_#in~arg.base_1|) (= v_Thread0_P0_~arg.offset_1 |v_Thread0_P0_#in~arg.offset_1|) (= v_~x~0_1 1) (= v_~y~0_1 1)) InVars {Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} OutVars{Thread0_P0_#in~arg.base=|v_Thread0_P0_#in~arg.base_1|, Thread0_P0_~arg.offset=v_Thread0_P0_~arg.offset_1, Thread0_P0_~arg.base=v_Thread0_P0_~arg.base_1, ~y~0=v_~y~0_1, ~x~0=v_~x~0_1, Thread0_P0_#in~arg.offset=|v_Thread0_P0_#in~arg.offset_1|} AuxVars[] AssignedVars[Thread0_P0_~arg.offset, Thread0_P0_~arg.base, ~y~0, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [530] L705-->L705-2: Formula: (or (= 0 (mod v_~x$r_buff0_thd1~0_4 256)) (= 0 (mod v_~x$w_buff0_used~0_3 256))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} OutVars{~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [533] L705-2-->L705-4: Formula: (and (or (= 0 (mod v_~x$w_buff1_used~0_4 256)) (= (mod v_~x$r_buff1_thd1~0_4 256) 0)) (= |v_Thread0_P0_#t~ite3_3| v_~x~0_2)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, ~x~0=v_~x~0_2} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_4, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_4, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_3|, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[Thread0_P0_#t~ite3] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [536] L705-4-->L705-5: Formula: (= |v_Thread0_P0_#t~ite4_4| |v_Thread0_P0_#t~ite3_4|) InVars {Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_4|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_4|} AuxVars[] AssignedVars[Thread0_P0_#t~ite4] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite3|=1, |Thread0_P0_#t~ite4|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [531] L705-5-->L706: Formula: (= v_~x~0_3 |v_Thread0_P0_#t~ite4_2|) InVars {Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_2|} OutVars{Thread0_P0_#t~ite4=|v_Thread0_P0_#t~ite4_3|, Thread0_P0_#t~ite3=|v_Thread0_P0_#t~ite3_1|, ~x~0=v_~x~0_3} AuxVars[] AssignedVars[Thread0_P0_#t~ite4, Thread0_P0_#t~ite3, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [535] L706-->L706-2: Formula: (and (= |v_Thread0_P0_#t~ite5_2| v_~x$w_buff0_used~0_7) (or (= 0 (mod v_~x$w_buff0_used~0_7 256)) (= (mod v_~x$r_buff0_thd1~0_8 256) 0))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_8, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_7} AuxVars[] AssignedVars[Thread0_P0_#t~ite5] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite5|=1, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [537] L706-2-->L707: Formula: (= v_~x$w_buff0_used~0_8 |v_Thread0_P0_#t~ite5_3|) InVars {Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_3|} OutVars{Thread0_P0_#t~ite5=|v_Thread0_P0_#t~ite5_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_8} AuxVars[] AssignedVars[Thread0_P0_#t~ite5, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [539] L707-->L707-2: Formula: (and (= |v_Thread0_P0_#t~ite6_2| v_~x$w_buff1_used~0_6) (or (= (mod v_~x$w_buff0_used~0_10 256) 0) (= (mod v_~x$r_buff0_thd1~0_10 256) 0)) (or (= 0 (mod v_~x$w_buff1_used~0_6 256)) (= (mod v_~x$r_buff1_thd1~0_7 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_6, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_10, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_10} AuxVars[] AssignedVars[Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite6|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 [540] L707-2-->L708: Formula: (= v_~x$w_buff1_used~0_7 |v_Thread0_P0_#t~ite6_3|) InVars {Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_7, Thread0_P0_#t~ite6=|v_Thread0_P0_#t~ite6_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread0_P0_#t~ite6] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 [556] L733-->L733-5: Formula: (and (not (= 0 (mod v_~x$r_buff0_thd2~0_12 256))) (= |v_Thread1_P1_#t~ite11_1| v_~x$w_buff0~0_4) (not (= 0 (mod v_~x$w_buff0_used~0_23 256)))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_4, Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_12, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_23} AuxVars[] AssignedVars[Thread1_P1_#t~ite11] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite11|=2, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 [558] L733-5-->L734: Formula: (= v_~x~0_5 |v_Thread1_P1_#t~ite11_2|) InVars {Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_2|} OutVars{Thread1_P1_#t~ite11=|v_Thread1_P1_#t~ite11_3|, ~x~0=v_~x~0_5, Thread1_P1_#t~ite10=|v_Thread1_P1_#t~ite10_1|} AuxVars[] AssignedVars[Thread1_P1_#t~ite10, Thread1_P1_#t~ite11, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [561] L734-->L734-2: Formula: (and (not (= (mod v_~x$w_buff0_used~0_12 256) 0)) (= |v_Thread1_P1_#t~ite12_1| 0) (not (= (mod v_~x$r_buff0_thd2~0_1 256) 0))) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_1|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_12} AuxVars[] AssignedVars[Thread1_P1_#t~ite12] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite12|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [564] L734-2-->L735: Formula: (= v_~x$w_buff0_used~0_14 |v_Thread1_P1_#t~ite12_3|) InVars {Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_3|} OutVars{Thread1_P1_#t~ite12=|v_Thread1_P1_#t~ite12_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_14} AuxVars[] AssignedVars[Thread1_P1_#t~ite12, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [566] L735-->L735-2: Formula: (and (= |v_Thread1_P1_#t~ite13_2| v_~x$w_buff1_used~0_11) (or (= 0 (mod v_~x$w_buff1_used~0_11 256)) (= 0 (mod v_~x$r_buff1_thd2~0_4 256))) (or (= (mod v_~x$r_buff0_thd2~0_4 256) 0) (= (mod v_~x$w_buff0_used~0_16 256) 0))) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_11, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_4, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_4, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_16} AuxVars[] AssignedVars[Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite13|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [567] L735-2-->L736: Formula: (= v_~x$w_buff1_used~0_12 |v_Thread1_P1_#t~ite13_3|) InVars {Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_3|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_12, Thread1_P1_#t~ite13=|v_Thread1_P1_#t~ite13_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, Thread1_P1_#t~ite13] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [569] L736-->L736-2: Formula: (and (or (= (mod v_~x$r_buff0_thd2~0_6 256) 0) (= 0 (mod v_~x$w_buff0_used~0_18 256))) (= |v_Thread1_P1_#t~ite14_2| v_~x$r_buff0_thd2~0_6)) InVars {~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} OutVars{Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_2|, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_18} AuxVars[] AssignedVars[Thread1_P1_#t~ite14] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite14|=1, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [570] L736-2-->L737: Formula: (= v_~x$r_buff0_thd2~0_7 |v_Thread1_P1_#t~ite14_3|) InVars {Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_3|} OutVars{~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_7, Thread1_P1_#t~ite14=|v_Thread1_P1_#t~ite14_4|} AuxVars[] AssignedVars[Thread1_P1_#t~ite14, ~x$r_buff0_thd2~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [572] L737-->L737-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_20 256) 0) (= (mod v_~x$r_buff0_thd2~0_9 256) 0)) (= |v_Thread1_P1_#t~ite15_2| v_~x$r_buff1_thd2~0_6) (or (= 0 (mod v_~x$r_buff1_thd2~0_6 256)) (= 0 (mod v_~x$w_buff1_used~0_14 256)))) InVars {~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_6, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_14, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_9, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_20} AuxVars[] AssignedVars[Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1_#t~ite15|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 [573] L737-2-->L742: Formula: (and (= v_~x$r_buff1_thd2~0_7 |v_Thread1_P1_#t~ite15_3|) (= v_~__unbuffered_cnt~0_3 (+ v_~__unbuffered_cnt~0_4 1))) InVars {Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_4} OutVars{~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_7, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_3, Thread1_P1_#t~ite15=|v_Thread1_P1_#t~ite15_4|} AuxVars[] AssignedVars[~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, Thread1_P1_#t~ite15] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [542] L708-->L708-2: Formula: (and (= |v_Thread0_P0_#t~ite7_2| v_~x$r_buff0_thd1~0_1) (or (= (mod v_~x$w_buff0_used~0_1 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_1 256)))) InVars {~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_2|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_1, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_1} AuxVars[] AssignedVars[Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite7|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [543] L708-2-->L709: Formula: (= v_~x$r_buff0_thd1~0_3 |v_Thread0_P0_#t~ite7_3|) InVars {Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_3|} OutVars{Thread0_P0_#t~ite7=|v_Thread0_P0_#t~ite7_4|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_3} AuxVars[] AssignedVars[~x$r_buff0_thd1~0, Thread0_P0_#t~ite7] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [545] L709-->L709-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_5 256) 0) (= 0 (mod v_~x$r_buff0_thd1~0_6 256))) (or (= (mod v_~x$r_buff1_thd1~0_3 256) 0) (= (mod v_~x$w_buff1_used~0_3 256) 0)) (= |v_Thread0_P0_#t~ite8_2| v_~x$r_buff1_thd1~0_3)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_3, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_6, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_3, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_2|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_5} AuxVars[] AssignedVars[Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread0_P0_#t~ite8|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 [546] L709-2-->L714: Formula: (and (= v_~x$r_buff1_thd1~0_5 |v_Thread0_P0_#t~ite8_3|) (= v_~__unbuffered_cnt~0_1 (+ v_~__unbuffered_cnt~0_2 1))) InVars {Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_2} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_1, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_5, Thread0_P0_#t~ite8=|v_Thread0_P0_#t~ite8_4|} AuxVars[] AssignedVars[~__unbuffered_cnt~0, ~x$r_buff1_thd1~0, Thread0_P0_#t~ite8] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [413] L758-1-->L762: Formula: (= v_~main$tmp_guard0~0_2 (ite (= (ite (= v_~__unbuffered_cnt~0_6 2) 1 0) 0) 0 1)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_6, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_2, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_2|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [500] L762-->L764: Formula: (not (= 0 (mod v_~main$tmp_guard0~0_3 256))) InVars {~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} OutVars{~main$tmp_guard0~0=v_~main$tmp_guard0~0_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [368] L764-->L764-2: Formula: (or (= 0 (mod v_~x$w_buff0_used~0_40 256)) (= 0 (mod v_~x$r_buff0_thd0~0_18 256))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_18, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_40} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [377] L764-2-->L764-4: Formula: (and (or (= (mod v_~x$w_buff1_used~0_26 256) 0) (= 0 (mod v_~x$r_buff1_thd0~0_12 256))) (= |v_ULTIMATE.start_main_#t~ite19_3| v_~x~0_10)) InVars {~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_26, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_12, ~x~0=v_~x~0_10, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [352] L764-4-->L764-5: Formula: (= |v_ULTIMATE.start_main_#t~ite20_3| |v_ULTIMATE.start_main_#t~ite19_4|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_3|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [354] L764-5-->L765: Formula: (= v_~x~0_11 |v_ULTIMATE.start_main_#t~ite20_5|) InVars {ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_5|} OutVars{ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_4|, ~x~0=v_~x~0_11, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite20, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [478] L765-->L765-2: Formula: (and (or (= 0 (mod v_~x$r_buff0_thd0~0_20 256)) (= (mod v_~x$w_buff0_used~0_42 256) 0)) (= |v_ULTIMATE.start_main_#t~ite21_3| v_~x$w_buff0_used~0_42)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_20, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_42} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [481] L765-2-->L766: Formula: (= v_~x$w_buff0_used~0_43 |v_ULTIMATE.start_main_#t~ite21_5|) InVars {ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_5|} OutVars{ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_4|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_43} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [421] L766-->L766-2: Formula: (and (or (= 0 (mod v_~x$r_buff1_thd0~0_14 256)) (= 0 (mod v_~x$w_buff1_used~0_28 256))) (or (= (mod v_~x$w_buff0_used~0_45 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_22 256))) (= |v_ULTIMATE.start_main_#t~ite22_3| v_~x$w_buff1_used~0_28)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_22, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_28, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_14, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_45} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [427] L766-2-->L767: Formula: (= v_~x$w_buff1_used~0_29 |v_ULTIMATE.start_main_#t~ite22_5|) InVars {ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_5|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_29, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_4|} AuxVars[] AssignedVars[~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite22] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [362] L767-->L767-2: Formula: (and (or (= (mod v_~x$w_buff0_used~0_47 256) 0) (= 0 (mod v_~x$r_buff0_thd0~0_24 256))) (= |v_ULTIMATE.start_main_#t~ite23_3| v_~x$r_buff0_thd0~0_24)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_24, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_3|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_47} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [519] L767-2-->L768: Formula: (= v_~x$r_buff0_thd0~0_25 |v_ULTIMATE.start_main_#t~ite23_5|) InVars {ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_5|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_25, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite23] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [469] L768-->L768-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite24_3| v_~x$r_buff1_thd0~0_16) (or (= (mod v_~x$w_buff1_used~0_31 256) 0) (= (mod v_~x$r_buff1_thd0~0_16 256) 0)) (or (= (mod v_~x$w_buff0_used~0_49 256) 0) (= (mod v_~x$r_buff0_thd0~0_27 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} OutVars{ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_3|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_27, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_31, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_16, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_49} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [450] L768-2-->L775: Formula: (and (= v_~weak$$choice2~0_8 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet26.base_3| |v_ULTIMATE.start_main_#t~nondet26.offset_3|)) 0 1)) (= v_~x$r_buff1_thd0~0_17 |v_ULTIMATE.start_main_#t~ite24_5|) (= v_~x$flush_delayed~0_5 v_~weak$$choice2~0_8) (= v_~weak$$choice0~0_2 (ite (= 0 (+ |v_ULTIMATE.start_main_#t~nondet25.base_3| |v_ULTIMATE.start_main_#t~nondet25.offset_3|)) 0 1)) (= v_~x$mem_tmp~0_3 v_~x~0_12)) InVars {ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_5|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_3|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_3|, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_3|, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_3|, ~x~0=v_~x~0_12} OutVars{~weak$$choice0~0=v_~weak$$choice0~0_2, ~x$flush_delayed~0=v_~x$flush_delayed~0_5, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_4|, ULTIMATE.start_main_#t~nondet26.base=|v_ULTIMATE.start_main_#t~nondet26.base_2|, ULTIMATE.start_main_#t~nondet26.offset=|v_ULTIMATE.start_main_#t~nondet26.offset_2|, ~x$mem_tmp~0=v_~x$mem_tmp~0_3, ULTIMATE.start_main_#t~nondet25.base=|v_ULTIMATE.start_main_#t~nondet25.base_2|, ~weak$$choice2~0=v_~weak$$choice2~0_8, ULTIMATE.start_main_#t~nondet25.offset=|v_ULTIMATE.start_main_#t~nondet25.offset_2|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_17, ~x~0=v_~x~0_12} AuxVars[] AssignedVars[~weak$$choice0~0, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~nondet26.base, ULTIMATE.start_main_#t~nondet26.offset, ~x$mem_tmp~0, ULTIMATE.start_main_#t~nondet25.base, ~weak$$choice2~0, ULTIMATE.start_main_#t~nondet25.offset, ~x$r_buff1_thd0~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [365] L775-->L775-5: Formula: (and (= |v_ULTIMATE.start_main_#t~ite28_2| v_~x~0_13) (let ((.cse0 (= (mod v_~x$r_buff0_thd0~0_28 256) 0))) (or (and (= (mod v_~x$r_buff1_thd0~0_18 256) 0) .cse0) (and (= (mod v_~x$w_buff1_used~0_32 256) 0) .cse0) (= (mod v_~x$w_buff0_used~0_50 256) 0)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_28, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_2|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_32, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_18, ~x~0=v_~x~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_50} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [353] L775-5-->L776: Formula: (= v_~x~0_14 |v_ULTIMATE.start_main_#t~ite28_5|) InVars {ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_5|} OutVars{ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_5|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_4|, ~x~0=v_~x~0_14} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_#t~ite27, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [475] L776-->L776-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite31_2| v_~x$w_buff0~0_8) (not (= (mod v_~weak$$choice2~0_9 256) 0))) InVars {~x$w_buff0~0=v_~x$w_buff0~0_8, ~weak$$choice2~0=v_~weak$$choice2~0_9} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_8, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_2|, ~weak$$choice2~0=v_~weak$$choice2~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [470] L776-8-->L777: Formula: (= v_~x$w_buff0~0_12 |v_ULTIMATE.start_main_#t~ite31_5|) InVars {ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_5|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_12, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_5|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_4|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_5|} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite31] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [418] L777-->L777-8: Formula: (and (not (= (mod v_~weak$$choice2~0_11 256) 0)) (= |v_ULTIMATE.start_main_#t~ite34_2| v_~x$w_buff1~0_7)) InVars {~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7} OutVars{~weak$$choice2~0=v_~weak$$choice2~0_11, ~x$w_buff1~0=v_~x$w_buff1~0_7, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [411] L777-8-->L778: Formula: (= v_~x$w_buff1~0_11 |v_ULTIMATE.start_main_#t~ite34_5|) InVars {ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_5|} OutVars{ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_5|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_5|, ~x$w_buff1~0=v_~x$w_buff1~0_11, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_4|} AuxVars[] AssignedVars[~x$w_buff1~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_#t~ite34] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [358] L778-->L778-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite37_4| v_~x$w_buff0_used~0_62) (not (= (mod v_~weak$$choice2~0_13 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} OutVars{ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_4|, ~weak$$choice2~0=v_~weak$$choice2~0_13, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_62} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite37] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [505] L778-8-->L779: Formula: (= v_~x$w_buff0_used~0_25 |v_ULTIMATE.start_main_#t~ite37_2|) InVars {ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_2|} OutVars{ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_1|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_1|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_1|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_25} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite37, ~x$w_buff0_used~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [466] L779-->L779-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite40_1| v_~x$w_buff1_used~0_16) (not (= (mod v_~weak$$choice2~0_1 256) 0))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_1, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_16} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_16, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_1|, ~weak$$choice2~0=v_~weak$$choice2~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [443] L779-8-->L780: Formula: (= v_~x$w_buff1_used~0_19 |v_ULTIMATE.start_main_#t~ite40_4|) InVars {ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_4|} OutVars{~x$w_buff1_used~0=v_~x$w_buff1_used~0_19, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_4|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_3|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~x$w_buff1_used~0, ULTIMATE.start_main_#t~ite38] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [409] L780-->L780-8: Formula: (and (= |v_ULTIMATE.start_main_#t~ite43_1| v_~x$r_buff0_thd0~0_6) (not (= 0 (mod v_~weak$$choice2~0_3 256)))) InVars {~weak$$choice2~0=v_~weak$$choice2~0_3, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_6, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_1|, ~weak$$choice2~0=v_~weak$$choice2~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [381] L780-8-->L781: Formula: (= v_~x$r_buff0_thd0~0_11 |v_ULTIMATE.start_main_#t~ite43_4|) InVars {ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_4|} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_11, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_4|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_3|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_4|} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [503] L781-->L781-8: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_5 256))) (= |v_ULTIMATE.start_main_#t~ite46_1| v_~x$r_buff1_thd0~0_6)) InVars {~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} OutVars{ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_1|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_6, ~weak$$choice2~0=v_~weak$$choice2~0_5} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [499] L781-8-->L783: Formula: (and (= v_~x$r_buff1_thd0~0_9 |v_ULTIMATE.start_main_#t~ite46_4|) (= v_~main$tmp_guard1~0_1 (ite (= 0 (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_2) (= 2 v_~x~0_6))) 1 0)) 0 1))) InVars {ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_4|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ~x~0=v_~x~0_6} OutVars{~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_2, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_3|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_1, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_9, ~x~0=v_~x~0_6, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_4|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ~x$r_buff1_thd0~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [404] L783-->L783-2: Formula: (and (= |v_ULTIMATE.start_main_#t~ite47_1| v_~x$mem_tmp~0_1) (not (= 0 (mod v_~x$flush_delayed~0_1 256)))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_1, ~x$mem_tmp~0=v_~x$mem_tmp~0_1} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_1|, ~x$mem_tmp~0=v_~x$mem_tmp~0_1, ~x$flush_delayed~0=v_~x$flush_delayed~0_1} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [384] L783-2-->L786: Formula: (and (= v_~x~0_8 |v_ULTIMATE.start_main_#t~ite47_4|) (= v_~x$flush_delayed~0_3 0)) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_4|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_3|, ~x$flush_delayed~0=v_~x$flush_delayed~0_3, ~x~0=v_~x~0_8} AuxVars[] AssignedVars[~x$flush_delayed~0, ULTIMATE.start_main_#t~ite47, ~x~0] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [364] L786-->L786-1: Formula: (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_1| (mod v_~main$tmp_guard1~0_2 256)) InVars {~main$tmp_guard1~0=v_~main$tmp_guard1~0_2} OutVars{~main$tmp_guard1~0=v_~main$tmp_guard1~0_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_#in~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [369] L786-1-->L4: Formula: true InVars {} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [406] L4-->L4-1: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_2 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_2, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_2|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [401] L4-1-->L4-2: Formula: (= v_ULTIMATE.start___VERIFIER_assert_~expression_3 0) InVars {ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_3} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 [397] L4-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_P0_thidvar0=0, Thread0_P0_~arg.base=0, Thread0_P0_~arg.offset=0, Thread1_P1___VERIFIER_assert_~expression=1, Thread1_P1_thidvar0=1, Thread1_P1_~arg.base=0, Thread1_P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_P0_#in~arg.base|=0, |Thread0_P0_#in~arg.offset|=0, |Thread1_P1_#in~arg.base|=0, |Thread1_P1_#in~arg.offset|=0, |Thread1_P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); srcloc: L757 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); srcloc: L757-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite27;havoc main_#t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite31;havoc main_#t~ite30;havoc main_#t~ite29; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite35;havoc main_#t~ite36;havoc main_#t~ite37; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite40;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite41;havoc main_#t~ite43; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite45;havoc main_#t~ite44;havoc main_#t~ite46;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 ~__unbuffered_cnt~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0] [?] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [?] -1 ~main$tmp_guard0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [?] -1 ~main$tmp_guard1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [?] -1 ~x~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [?] -1 ~x$flush_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [?] -1 ~x$mem_tmp~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff0_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [?] -1 ~x$r_buff1_thd2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [?] -1 ~x$read_delayed~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [?] -1 ~x$w_buff0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff0_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [?] -1 ~x$w_buff1~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~x$w_buff1_used~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [?] -1 ~y~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice0~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 ~weak$$choice2~0 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); srcloc: L755 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); srcloc: L755-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 0 P0(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17; VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); srcloc: L757 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 SUMMARY for call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); srcloc: L757-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] FORK -1 fork 1 P1(0, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~x$w_buff1~0 := ~x$w_buff0~0;~x$w_buff0~0 := 2;~x$w_buff1_used~0 := ~x$w_buff0_used~0;~x$w_buff0_used~0 := 1;__VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0);havoc __VERIFIER_assert_~expression;__VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0;~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0;~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0;~x$r_buff0_thd2~0 := 1;~__unbuffered_p1_EAX~0 := ~y~0; VAL [P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset;~y~0 := 1;~x~0 := 1; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256);#t~ite3 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 #t~ite4 := #t~ite3; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite3|=1, |P0_#t~ite4|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x~0 := #t~ite4;havoc #t~ite3;havoc #t~ite4; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite5 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite5|=1, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff0_used~0 := #t~ite5;havoc #t~ite5; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite6 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite6|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 1 ~x$w_buff1_used~0 := #t~ite6;havoc #t~ite6; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite11 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite11|=2, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [?] 0 ~x~0 := #t~ite11;havoc #t~ite11;havoc #t~ite10; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256;#t~ite12 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite12|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff0_used~0 := #t~ite12;havoc #t~ite12; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite13 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite13|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$w_buff1_used~0 := #t~ite13;havoc #t~ite13; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256);#t~ite14 := ~x$r_buff0_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite14|=1, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff0_thd2~0 := #t~ite14;havoc #t~ite14; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256));#t~ite15 := ~x$r_buff1_thd2~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1_#t~ite15|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 0 ~x$r_buff1_thd2~0 := #t~ite15;havoc #t~ite15;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256);#t~ite7 := ~x$r_buff0_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite7|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff0_thd1~0 := #t~ite7;havoc #t~ite7; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256));#t~ite8 := ~x$r_buff1_thd1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P0_#t~ite8|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] 1 ~x$r_buff1_thd1~0 := #t~ite8;havoc #t~ite8;~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc main_#t~nondet18;~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256);main_#t~ite19 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 main_#t~ite20 := main_#t~ite19; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite19|=2, |ULTIMATE.start_main_#t~ite20|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite20;havoc main_#t~ite19;havoc main_#t~ite20; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite21 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite21|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite21;havoc main_#t~ite21; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite22 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite22|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite22;havoc main_#t~ite22; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256);main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite23|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite23;havoc main_#t~ite23; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256));main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite24|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite24;havoc main_#t~ite24;~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1);havoc main_#t~nondet25.base, main_#t~nondet25.offset;~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1);havoc main_#t~nondet26.base, main_#t~nondet26.offset;~x$flush_delayed~0 := ~weak$$choice2~0;~x$mem_tmp~0 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256);main_#t~ite28 := ~x~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite28|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite28;havoc main_#t~ite27;havoc main_#t~ite28; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite31 := ~x$w_buff0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite31|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0~0 := main_#t~ite31;havoc main_#t~ite31;havoc main_#t~ite30;havoc main_#t~ite29; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite34 := ~x$w_buff1~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite34|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1~0 := main_#t~ite34;havoc main_#t~ite33;havoc main_#t~ite32;havoc main_#t~ite34; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite37 := ~x$w_buff0_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite37|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff0_used~0 := main_#t~ite37;havoc main_#t~ite35;havoc main_#t~ite36;havoc main_#t~ite37; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite40 := ~x$w_buff1_used~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite40|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$w_buff1_used~0 := main_#t~ite40;havoc main_#t~ite40;havoc main_#t~ite38;havoc main_#t~ite39; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite43|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff0_thd0~0 := main_#t~ite43;havoc main_#t~ite42;havoc main_#t~ite41;havoc main_#t~ite43; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~weak$$choice2~0 % 256;main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite46|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x$r_buff1_thd0~0 := main_#t~ite46;havoc main_#t~ite45;havoc main_#t~ite44;havoc main_#t~ite46;~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 != ~x$flush_delayed~0 % 256;main_#t~ite47 := ~x$mem_tmp~0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ite47|=2, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 ~x~0 := main_#t~ite47;havoc main_#t~ite47;~x$flush_delayed~0 := 0; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 havoc __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume 0 == __VERIFIER_assert_~expression; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 assume !false; VAL [P0_~arg.base=0, P0_~arg.offset=0, P1___VERIFIER_assert_~expression=1, P1_~arg.base=0, P1_~arg.offset=0, ULTIMATE.start___VERIFIER_assert_~expression=0, |#NULL.base|=0, |#NULL.offset|=0, |P0_#in~arg.base|=0, |P0_#in~arg.offset|=0, |P1_#in~arg.base|=0, |P1_#in~arg.offset|=0, |P1___VERIFIER_assert_#in~expression|=1, |ULTIMATE.start___VERIFIER_assert_#in~expression|=0, |ULTIMATE.start_main_~#t1457~0.base|=5, |ULTIMATE.start_main_~#t1457~0.offset|=0, |ULTIMATE.start_main_~#t1458~0.base|=6, |ULTIMATE.start_main_~#t1458~0.offset|=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] -1 call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] -1 call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L734] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L771] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L772] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 assume 0 != ~weak$$choice2~0 % 256; [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 assume 0 != ~weak$$choice2~0 % 256; [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 assume 0 != ~x$flush_delayed~0 % 256; [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0.base, ~x$read_delayed_var~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25.base, main_#t~nondet25.offset, main_#t~nondet26.base, main_#t~nondet26.offset, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0.base, main_~#t1457~0.offset, main_~#t1458~0.base, main_~#t1458~0.offset; VAL [#NULL.base=0, #NULL.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] -1 call main_~#t1457~0.base, main_~#t1457~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 call write~int(0, main_~#t1457~0.base, main_~#t1457~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] -1 call main_~#t1458~0.base, main_~#t1458~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] -1 call write~int(1, main_~#t1458~0.base, main_~#t1458~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1(0, 0); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] 0 assume !(0 == __VERIFIER_assert_~expression); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256); [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 assume 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256; [L734] 0 #t~ite12 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256); [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)); [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256); [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)); [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 assume !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256); [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 assume !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256); [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 assume !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)); [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25.base + main_#t~nondet25.offset then 0 else 1); [L771] -1 havoc main_#t~nondet25.base, main_#t~nondet25.offset; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26.base + main_#t~nondet26.offset then 0 else 1); [L772] -1 havoc main_#t~nondet26.base, main_#t~nondet26.offset; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 assume (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256); [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 assume 0 != ~weak$$choice2~0 % 256; [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 assume 0 != ~weak$$choice2~0 % 256; [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 assume 0 != ~weak$$choice2~0 % 256; [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 assume 0 != ~weak$$choice2~0 % 256; [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 assume 0 != ~weak$$choice2~0 % 256; [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 assume 0 != ~weak$$choice2~0 % 256; [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 assume 0 != ~x$flush_delayed~0 % 256; [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assume 0 == __VERIFIER_assert_~expression; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg.base=0, #in~arg.base=0, #in~arg.offset=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0.base=5, main_~#t1457~0.offset=0, main_~#t1458~0.base=6, main_~#t1458~0.offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg.base=0, ~arg.base=0, ~arg.offset=0, ~arg.offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0.base=0, ~x$read_delayed_var~0.offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0, main_~#t1458~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, main_~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call main_~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, main_~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L771] -1 havoc main_#t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L772] -1 havoc main_#t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [?] -1 havoc main_#t~nondet17, main_#t~nondet18, main_#t~ite20, main_#t~ite19, main_#t~ite21, main_#t~ite22, main_#t~ite23, main_#t~ite24, main_#t~nondet25, main_#t~nondet26, main_#t~ite28, main_#t~ite27, main_#t~ite31, main_#t~ite30, main_#t~ite29, main_#t~ite34, main_#t~ite33, main_#t~ite32, main_#t~ite37, main_#t~ite36, main_#t~ite35, main_#t~ite40, main_#t~ite39, main_#t~ite38, main_#t~ite43, main_#t~ite42, main_#t~ite41, main_#t~ite46, main_#t~ite45, main_#t~ite44, main_#t~ite47, main_~#t1457~0, main_~#t1458~0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call main_~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, main_~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc main_#t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call main_~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, main_~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L723] 0 __VERIFIER_assert_#in~expression := (if !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$w_buff0_used~0 % 256) then 1 else 0); [L723] 0 havoc __VERIFIER_assert_~expression; [L4] 0 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == __VERIFIER_assert_~expression) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite11=2, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite12=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite13=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite14=1, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite15=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc main_#t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 main_#t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 main_#t~ite20 := main_#t~ite19; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite19=2, main_#t~ite20=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := main_#t~ite20; [L764] -1 havoc main_#t~ite19; [L764] -1 havoc main_#t~ite20; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 main_#t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite21=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := main_#t~ite21; [L765] -1 havoc main_#t~ite21; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 main_#t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite22=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := main_#t~ite22; [L766] -1 havoc main_#t~ite22; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 main_#t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite23=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := main_#t~ite23; [L767] -1 havoc main_#t~ite23; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 main_#t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite24=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := main_#t~ite24; [L768] -1 havoc main_#t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == main_#t~nondet25!base + main_#t~nondet25!offset then 0 else 1); [L771] -1 havoc main_#t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == main_#t~nondet26!base + main_#t~nondet26!offset then 0 else 1); [L772] -1 havoc main_#t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 main_#t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite28=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := main_#t~ite28; [L775] -1 havoc main_#t~ite27; [L775] -1 havoc main_#t~ite28; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 main_#t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite31=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := main_#t~ite31; [L776] -1 havoc main_#t~ite31; [L776] -1 havoc main_#t~ite30; [L776] -1 havoc main_#t~ite29; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 main_#t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite34=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := main_#t~ite34; [L777] -1 havoc main_#t~ite33; [L777] -1 havoc main_#t~ite32; [L777] -1 havoc main_#t~ite34; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 main_#t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite37=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := main_#t~ite37; [L778] -1 havoc main_#t~ite35; [L778] -1 havoc main_#t~ite36; [L778] -1 havoc main_#t~ite37; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 main_#t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite40=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := main_#t~ite40; [L779] -1 havoc main_#t~ite40; [L779] -1 havoc main_#t~ite38; [L779] -1 havoc main_#t~ite39; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 main_#t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite43=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := main_#t~ite43; [L780] -1 havoc main_#t~ite42; [L780] -1 havoc main_#t~ite41; [L780] -1 havoc main_#t~ite43; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 main_#t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite46=0, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := main_#t~ite46; [L781] -1 havoc main_#t~ite45; [L781] -1 havoc main_#t~ite44; [L781] -1 havoc main_#t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 main_#t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_#t~ite47=2, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := main_#t~ite47; [L783] -1 havoc main_#t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 __VERIFIER_assert_#in~expression := ~main$tmp_guard1~0 % 256; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L786] -1 havoc __VERIFIER_assert_~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 __VERIFIER_assert_~expression := __VERIFIER_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == __VERIFIER_assert_~expression VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!base=0, #in~arg!offset=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, __VERIFIER_assert_#in~expression=0, __VERIFIER_assert_#in~expression=1, __VERIFIER_assert_~expression=0, __VERIFIER_assert_~expression=1, main_~#t1457~0!base=5, main_~#t1457~0!offset=0, main_~#t1458~0!base=6, main_~#t1458~0!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!base=0, ~arg!offset=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, ~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call ~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, ~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc #t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := #t~ite20; [L764] -1 havoc #t~ite19; [L764] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := #t~ite21; [L765] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := #t~ite22; [L766] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L767] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L768] -1 havoc #t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L771] -1 havoc #t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L772] -1 havoc #t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := #t~ite28; [L775] -1 havoc #t~ite27; [L775] -1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := #t~ite31; [L776] -1 havoc #t~ite31; [L776] -1 havoc #t~ite30; [L776] -1 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := #t~ite34; [L777] -1 havoc #t~ite33; [L777] -1 havoc #t~ite32; [L777] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := #t~ite37; [L778] -1 havoc #t~ite35; [L778] -1 havoc #t~ite36; [L778] -1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := #t~ite40; [L779] -1 havoc #t~ite40; [L779] -1 havoc #t~ite38; [L779] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L780] -1 havoc #t~ite42; [L780] -1 havoc #t~ite41; [L780] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L781] -1 havoc #t~ite45; [L781] -1 havoc #t~ite44; [L781] -1 havoc #t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := #t~ite47; [L783] -1 havoc #t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L671] -1 ~__unbuffered_cnt~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0] [L673] -1 ~__unbuffered_p1_EAX~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0] [L674] -1 ~main$tmp_guard0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0] [L675] -1 ~main$tmp_guard1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0] [L677] -1 ~x~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x~0=0] [L678] -1 ~x$flush_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x~0=0] [L679] -1 ~x$mem_tmp~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x~0=0] [L680] -1 ~x$r_buff0_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x~0=0] [L681] -1 ~x$r_buff0_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x~0=0] [L682] -1 ~x$r_buff0_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x~0=0] [L683] -1 ~x$r_buff1_thd0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x~0=0] [L684] -1 ~x$r_buff1_thd1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x~0=0] [L685] -1 ~x$r_buff1_thd2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x~0=0] [L686] -1 ~x$read_delayed~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed~0=0, ~x~0=0] [L687] -1 ~x$read_delayed_var~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x~0=0] [L688] -1 ~x$w_buff0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0~0=0, ~x~0=0] [L689] -1 ~x$w_buff0_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x~0=0] [L690] -1 ~x$w_buff1~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1~0=0, ~x~0=0] [L691] -1 ~x$w_buff1_used~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0] [L693] -1 ~y~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L694] -1 ~weak$$choice0~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L695] -1 ~weak$$choice2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L755] FCALL -1 call ~#t1457~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FCALL -1 call write~int(0, ~#t1457~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] FORK -1 fork 0 P0({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L756] -1 havoc #t~nondet17; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L757] FCALL -1 call ~#t1458~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FCALL -1 call write~int(1, ~#t1458~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L758] FORK -1 fork 1 P1({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=0, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L716-L743] 0 ~arg := #in~arg; [L719] 0 ~x$w_buff1~0 := ~x$w_buff0~0; [L720] 0 ~x$w_buff0~0 := 2; [L721] 0 ~x$w_buff1_used~0 := ~x$w_buff0_used~0; [L722] 0 ~x$w_buff0_used~0 := 1; [L4] 0 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L4] COND FALSE 0 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=0, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L724] 0 ~x$r_buff1_thd0~0 := ~x$r_buff0_thd0~0; [L725] 0 ~x$r_buff1_thd1~0 := ~x$r_buff0_thd1~0; [L726] 0 ~x$r_buff1_thd2~0 := ~x$r_buff0_thd2~0; [L727] 0 ~x$r_buff0_thd2~0 := 1; [L730] 0 ~__unbuffered_p1_EAX~0 := ~y~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=0, ~y~0=0] [L696-L715] 1 ~arg := #in~arg; [L699] 1 ~y~0 := 1; [L702] 1 ~x~0 := 1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] COND FALSE 1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256) [L705] 1 #t~ite3 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 #t~ite4 := #t~ite3; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite3=1, #t~ite4=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L705] 1 ~x~0 := #t~ite4; [L705] 1 havoc #t~ite3; [L705] 1 havoc #t~ite4; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L706] 1 #t~ite5 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite5=1, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L706] 1 ~x$w_buff0_used~0 := #t~ite5; [L706] 1 havoc #t~ite5; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L707] 1 #t~ite6 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite6=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L707] 1 ~x$w_buff1_used~0 := #t~ite6; [L707] 1 havoc #t~ite6; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L733] 0 #t~ite11 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=1, ~y~0=1] [L733] 0 ~x~0 := #t~ite11; [L733] 0 havoc #t~ite11; [L733] 0 havoc #t~ite10; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] COND TRUE 0 0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256 [L734] 0 #t~ite12 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=1, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L734] 0 ~x$w_buff0_used~0 := #t~ite12; [L734] 0 havoc #t~ite12; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L735] 0 #t~ite13 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L735] 0 ~x$w_buff1_used~0 := #t~ite13; [L735] 0 havoc #t~ite13; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] COND FALSE 0 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) [L736] 0 #t~ite14 := ~x$r_buff0_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L736] 0 ~x$r_buff0_thd2~0 := #t~ite14; [L736] 0 havoc #t~ite14; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] COND FALSE 0 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd2~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd2~0 % 256)) [L737] 0 #t~ite15 := ~x$r_buff1_thd2~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=0, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L737] 0 ~x$r_buff1_thd2~0 := #t~ite15; [L737] 0 havoc #t~ite15; [L740] 0 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] COND FALSE 1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) [L708] 1 #t~ite7 := ~x$r_buff0_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite7=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L708] 1 ~x$r_buff0_thd1~0 := #t~ite7; [L708] 1 havoc #t~ite7; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] COND FALSE 1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd1~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd1~0 % 256)) [L709] 1 #t~ite8 := ~x$r_buff1_thd1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~ite8=0, ~__unbuffered_cnt~0=1, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L709] 1 ~x$r_buff1_thd1~0 := #t~ite8; [L709] 1 havoc #t~ite8; [L712] 1 ~__unbuffered_cnt~0 := 1 + ~__unbuffered_cnt~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=0, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L758] -1 havoc #t~nondet18; [L760] -1 ~main$tmp_guard0~0 := (if 0 == (if 2 == ~__unbuffered_cnt~0 then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L762] -1 assume 0 != ~main$tmp_guard0~0 % 256; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] COND FALSE -1 !(0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256) [L764] -1 #t~ite19 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 #t~ite20 := #t~ite19; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L764] -1 ~x~0 := #t~ite20; [L764] -1 havoc #t~ite19; [L764] -1 havoc #t~ite20; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L765] -1 #t~ite21 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L765] -1 ~x$w_buff0_used~0 := #t~ite21; [L765] -1 havoc #t~ite21; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L766] -1 #t~ite22 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L766] -1 ~x$w_buff1_used~0 := #t~ite22; [L766] -1 havoc #t~ite22; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] COND FALSE -1 !(0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) [L767] -1 #t~ite23 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L767] -1 ~x$r_buff0_thd0~0 := #t~ite23; [L767] -1 havoc #t~ite23; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] COND FALSE -1 !((0 != ~x$w_buff0_used~0 % 256 && 0 != ~x$r_buff0_thd0~0 % 256) || (0 != ~x$w_buff1_used~0 % 256 && 0 != ~x$r_buff1_thd0~0 % 256)) [L768] -1 #t~ite24 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=0, ~x$flush_delayed~0=0, ~x$mem_tmp~0=0, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L768] -1 ~x$r_buff1_thd0~0 := #t~ite24; [L768] -1 havoc #t~ite24; [L771] -1 ~weak$$choice0~0 := (if 0 == #t~nondet25!base + #t~nondet25!offset then 0 else 1); [L771] -1 havoc #t~nondet25; [L772] -1 ~weak$$choice2~0 := (if 0 == #t~nondet26!base + #t~nondet26!offset then 0 else 1); [L772] -1 havoc #t~nondet26; [L773] -1 ~x$flush_delayed~0 := ~weak$$choice2~0; [L774] -1 ~x$mem_tmp~0 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] COND TRUE -1 (0 == ~x$w_buff0_used~0 % 256 || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$w_buff1_used~0 % 256)) || (0 == ~x$r_buff0_thd0~0 % 256 && 0 == ~x$r_buff1_thd0~0 % 256) [L775] -1 #t~ite28 := ~x~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L775] -1 ~x~0 := #t~ite28; [L775] -1 havoc #t~ite27; [L775] -1 havoc #t~ite28; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L776] -1 #t~ite31 := ~x$w_buff0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L776] -1 ~x$w_buff0~0 := #t~ite31; [L776] -1 havoc #t~ite31; [L776] -1 havoc #t~ite30; [L776] -1 havoc #t~ite29; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L777] -1 #t~ite34 := ~x$w_buff1~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L777] -1 ~x$w_buff1~0 := #t~ite34; [L777] -1 havoc #t~ite33; [L777] -1 havoc #t~ite32; [L777] -1 havoc #t~ite34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L778] -1 #t~ite37 := ~x$w_buff0_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L778] -1 ~x$w_buff0_used~0 := #t~ite37; [L778] -1 havoc #t~ite35; [L778] -1 havoc #t~ite36; [L778] -1 havoc #t~ite37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L779] -1 #t~ite40 := ~x$w_buff1_used~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L779] -1 ~x$w_buff1_used~0 := #t~ite40; [L779] -1 havoc #t~ite40; [L779] -1 havoc #t~ite38; [L779] -1 havoc #t~ite39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L780] -1 #t~ite43 := ~x$r_buff0_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L780] -1 ~x$r_buff0_thd0~0 := #t~ite43; [L780] -1 havoc #t~ite42; [L780] -1 havoc #t~ite41; [L780] -1 havoc #t~ite43; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] COND TRUE -1 0 != ~weak$$choice2~0 % 256 [L781] -1 #t~ite46 := ~x$r_buff1_thd0~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L781] -1 ~x$r_buff1_thd0~0 := #t~ite46; [L781] -1 havoc #t~ite45; [L781] -1 havoc #t~ite44; [L781] -1 havoc #t~ite46; [L782] -1 ~main$tmp_guard1~0 := (if 0 == (if !(2 == ~x~0 && 0 == ~__unbuffered_p1_EAX~0) then 1 else 0) then 0 else 1); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] COND TRUE -1 0 != ~x$flush_delayed~0 % 256 [L783] -1 #t~ite47 := ~x$mem_tmp~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=1, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L783] -1 ~x~0 := #t~ite47; [L783] -1 havoc #t~ite47; [L784] -1 ~x$flush_delayed~0 := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L4] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~__unbuffered_cnt~0=2, ~__unbuffered_p1_EAX~0=0, ~arg!base=0, ~arg!offset=0, ~main$tmp_guard0~0=1, ~main$tmp_guard1~0=0, ~weak$$choice0~0=0, ~weak$$choice2~0=1, ~x$flush_delayed~0=0, ~x$mem_tmp~0=2, ~x$r_buff0_thd0~0=0, ~x$r_buff0_thd1~0=0, ~x$r_buff0_thd2~0=1, ~x$r_buff1_thd0~0=0, ~x$r_buff1_thd1~0=0, ~x$r_buff1_thd2~0=0, ~x$read_delayed_var~0!base=0, ~x$read_delayed_var~0!offset=0, ~x$read_delayed~0=0, ~x$w_buff0_used~0=0, ~x$w_buff0~0=2, ~x$w_buff1_used~0=0, ~x$w_buff1~0=0, ~x~0=2, ~y~0=1] [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L674] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0] [L675] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L677] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L678] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L679] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L680] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L681] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L682] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L683] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L684] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L685] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L686] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L687] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L688] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L689] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L690] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L691] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L693] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L694] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L695] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t1457; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t1457, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L757] -1 pthread_t t1458; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L758] FCALL, FORK -1 pthread_create(&t1458, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L719] 0 x$w_buff1 = x$w_buff0 [L720] 0 x$w_buff0 = 2 [L721] 0 x$w_buff1_used = x$w_buff0_used [L722] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L724] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 0 x$r_buff0_thd2 = (_Bool)1 [L730] 0 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L699] 1 y = 1 [L702] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L706] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L707] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L735] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L736] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L736] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L737] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L737] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L740] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L709] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L709] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L712] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L760] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L765] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L767] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L768] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L771] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L772] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L773] -1 x$flush_delayed = weak$$choice2 [L774] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L776] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L777] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L778] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L778] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L779] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L779] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L780] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L781] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L781] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L782] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] -1 x = x$flush_delayed ? x$mem_tmp : x [L784] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] ----- [2018-11-23 05:47:06,097 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_0be5bf48-9d15-4655-b306-04d0d34e1453/bin-2019/utaipan/witness.graphml [2018-11-23 05:47:06,098 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:47:06,098 INFO L168 Benchmark]: Toolchain (without parser) took 18984.92 ms. Allocated memory was 1.0 GB in the beginning and 2.3 GB in the end (delta: 1.2 GB). Free memory was 951.1 MB in the beginning and 710.7 MB in the end (delta: 240.4 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,099 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:47:06,100 INFO L168 Benchmark]: CACSL2BoogieTranslator took 428.41 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.8 MB). Free memory was 951.1 MB in the beginning and 1.1 GB in the end (delta: -174.1 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,100 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,100 INFO L168 Benchmark]: Boogie Preprocessor took 20.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:47:06,101 INFO L168 Benchmark]: RCFGBuilder took 449.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,101 INFO L168 Benchmark]: TraceAbstraction took 13944.10 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.1 GB in the beginning and 810.6 MB in the end (delta: 261.9 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,101 INFO L168 Benchmark]: Witness Printer took 4103.79 ms. Allocated memory is still 2.3 GB. Free memory was 810.6 MB in the beginning and 710.7 MB in the end (delta: 99.9 MB). Peak memory consumption was 99.9 MB. Max. memory is 11.5 GB. [2018-11-23 05:47:06,103 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 428.41 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.8 MB). Free memory was 951.1 MB in the beginning and 1.1 GB in the end (delta: -174.1 MB). Peak memory consumption was 38.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 34.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 20.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 449.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 46.1 MB). Peak memory consumption was 46.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 13944.10 ms. Allocated memory was 1.2 GB in the beginning and 2.3 GB in the end (delta: 1.1 GB). Free memory was 1.1 GB in the beginning and 810.6 MB in the end (delta: 261.9 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 4103.79 ms. Allocated memory is still 2.3 GB. Free memory was 810.6 MB in the beginning and 710.7 MB in the end (delta: 99.9 MB). Peak memory consumption was 99.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L671] -1 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L673] -1 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0] [L674] -1 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0] [L675] -1 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L677] -1 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L678] -1 _Bool x$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0] [L679] -1 int x$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0] [L680] -1 _Bool x$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0] [L681] -1 _Bool x$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0] [L682] -1 _Bool x$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0] [L683] -1 _Bool x$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0] [L684] -1 _Bool x$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0] [L685] -1 _Bool x$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0] [L686] -1 _Bool x$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0] [L687] -1 int *x$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}] [L688] -1 int x$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0] [L689] -1 _Bool x$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0] [L690] -1 int x$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0] [L691] -1 _Bool x$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0] [L693] -1 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L694] -1 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L695] -1 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L755] -1 pthread_t t1457; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] FCALL, FORK -1 pthread_create(&t1457, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L757] -1 pthread_t t1458; VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L758] FCALL, FORK -1 pthread_create(&t1458, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L719] 0 x$w_buff1 = x$w_buff0 [L720] 0 x$w_buff0 = 2 [L721] 0 x$w_buff1_used = x$w_buff0_used [L722] 0 x$w_buff0_used = (_Bool)1 [L4] COND FALSE 0 !(!expression) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L724] 0 x$r_buff1_thd0 = x$r_buff0_thd0 [L725] 0 x$r_buff1_thd1 = x$r_buff0_thd1 [L726] 0 x$r_buff1_thd2 = x$r_buff0_thd2 [L727] 0 x$r_buff0_thd2 = (_Bool)1 [L730] 0 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L699] 1 y = 1 [L702] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L705] EXPR 1 x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x)=1, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x=1, y=1] [L705] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L706] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L706] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L707] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L707] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L733] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L733] 0 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L734] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L734] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L735] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L735] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L736] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L736] 0 x$r_buff0_thd2 = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$r_buff0_thd2 [L737] EXPR 0 x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L737] 0 x$r_buff1_thd2 = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$r_buff1_thd2 [L740] 0 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L708] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L709] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L709] 1 x$r_buff1_thd1 = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$r_buff1_thd1 [L712] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L760] -1 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L764] -1 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L765] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L765] -1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L766] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L766] -1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L767] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L767] -1 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L768] EXPR -1 x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L768] -1 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L771] -1 weak$$choice0 = __VERIFIER_nondet_pointer() [L772] -1 weak$$choice2 = __VERIFIER_nondet_pointer() [L773] -1 x$flush_delayed = weak$$choice2 [L774] -1 x$mem_tmp = x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] EXPR -1 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L775] -1 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L776] EXPR -1 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L776] -1 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L777] EXPR -1 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L777] -1 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L778] EXPR -1 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L778] -1 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L779] EXPR -1 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L779] -1 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L780] EXPR -1 weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L780] -1 x$r_buff0_thd0 = weak$$choice2 ? x$r_buff0_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff0_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0)) [L781] EXPR -1 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L781] -1 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L782] -1 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 0) VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] EXPR -1 x$flush_delayed ? x$mem_tmp : x VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L783] -1 x = x$flush_delayed ? x$mem_tmp : x [L784] -1 x$flush_delayed = (_Bool)0 VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] COND TRUE -1 !expression VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L4] -1 __VERIFIER_error() VAL [__unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=1, x=2, x$flush_delayed=0, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 179 locations, 3 error locations. UNSAFE Result, 13.8s OverallTime, 25 OverallIterations, 1 TraceHistogramMax, 5.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4907 SDtfs, 4375 SDslu, 10892 SDs, 0 SdLazy, 4434 SolverSat, 246 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 217 GetRequests, 60 SyntacticMatches, 17 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 1.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=37141occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 2.9s AutomataMinimizationTime, 24 MinimizatonAttempts, 58643 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.5s InterpolantComputationTime, 2089 NumberOfCodeBlocks, 2089 NumberOfCodeBlocksAsserted, 25 NumberOfCheckSat, 1971 ConstructedInterpolants, 0 QuantifiedInterpolants, 411830 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 24 InterpolantComputations, 24 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...