./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i -s /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash be78f24495f6395b0c8bd7d622003423e0349301 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 07:22:30,465 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 07:22:30,466 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 07:22:30,473 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 07:22:30,473 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 07:22:30,474 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 07:22:30,475 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 07:22:30,476 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 07:22:30,477 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 07:22:30,478 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 07:22:30,478 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 07:22:30,478 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 07:22:30,479 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 07:22:30,480 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 07:22:30,481 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 07:22:30,481 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 07:22:30,482 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 07:22:30,483 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 07:22:30,484 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 07:22:30,486 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 07:22:30,486 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 07:22:30,487 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 07:22:30,489 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 07:22:30,489 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 07:22:30,489 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 07:22:30,490 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 07:22:30,491 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 07:22:30,491 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 07:22:30,492 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 07:22:30,492 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 07:22:30,493 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 07:22:30,493 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 07:22:30,493 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 07:22:30,493 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 07:22:30,494 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 07:22:30,494 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 07:22:30,495 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2018-11-23 07:22:30,505 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 07:22:30,505 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 07:22:30,505 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * User list type=DISABLED [2018-11-23 07:22:30,506 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * Explicit value domain=true [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * Octagon Domain=false [2018-11-23 07:22:30,506 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-11-23 07:22:30,507 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-11-23 07:22:30,507 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-11-23 07:22:30,507 INFO L133 SettingsManager]: * Interval Domain=false [2018-11-23 07:22:30,507 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 07:22:30,508 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 07:22:30,509 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 07:22:30,509 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 07:22:30,509 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 07:22:30,509 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 07:22:30,509 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 07:22:30,509 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:22:30,510 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-11-23 07:22:30,510 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 07:22:30,511 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 07:22:30,511 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-23 07:22:30,511 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> be78f24495f6395b0c8bd7d622003423e0349301 [2018-11-23 07:22:30,534 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 07:22:30,543 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 07:22:30,545 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 07:22:30,546 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 07:22:30,547 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 07:22:30,547 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/../../sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i [2018-11-23 07:22:30,586 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/data/2ac448d94/d77e6b7eaf7b4f419d97c7cef436060b/FLAG0276d46ca [2018-11-23 07:22:31,075 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 07:22:31,076 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/sv-benchmarks/c/ldv-races/race-3_2-container_of-global_false-unreach-call.i [2018-11-23 07:22:31,089 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/data/2ac448d94/d77e6b7eaf7b4f419d97c7cef436060b/FLAG0276d46ca [2018-11-23 07:22:31,567 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/data/2ac448d94/d77e6b7eaf7b4f419d97c7cef436060b [2018-11-23 07:22:31,569 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 07:22:31,570 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 07:22:31,571 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 07:22:31,571 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 07:22:31,573 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 07:22:31,573 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:22:31" (1/1) ... [2018-11-23 07:22:31,575 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60445fa0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:31, skipping insertion in model container [2018-11-23 07:22:31,575 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 07:22:31" (1/1) ... [2018-11-23 07:22:31,582 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 07:22:31,620 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 07:22:32,093 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:22:32,100 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 07:22:32,207 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 07:22:32,443 INFO L195 MainTranslator]: Completed translation [2018-11-23 07:22:32,444 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32 WrapperNode [2018-11-23 07:22:32,444 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 07:22:32,444 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 07:22:32,444 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 07:22:32,445 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 07:22:32,451 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,472 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,493 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 07:22:32,493 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 07:22:32,493 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 07:22:32,493 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 07:22:32,501 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,501 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,505 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,505 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,514 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,516 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,519 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... [2018-11-23 07:22:32,523 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 07:22:32,523 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 07:22:32,523 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 07:22:32,523 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 07:22:32,524 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 07:22:32,567 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 07:22:32,567 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 07:22:32,567 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 07:22:32,567 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-23 07:22:32,568 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 07:22:32,568 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 07:22:32,568 INFO L130 BoogieDeclarations]: Found specification of procedure my_callback [2018-11-23 07:22:32,568 INFO L138 BoogieDeclarations]: Found implementation of procedure my_callback [2018-11-23 07:22:32,568 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 07:22:32,568 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 07:22:32,569 WARN L198 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2018-11-23 07:22:33,044 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 07:22:33,044 INFO L280 CfgBuilder]: Removed 24 assue(true) statements. [2018-11-23 07:22:33,045 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:22:33 BoogieIcfgContainer [2018-11-23 07:22:33,045 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 07:22:33,046 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 07:22:33,046 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 07:22:33,048 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 07:22:33,049 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 07:22:31" (1/3) ... [2018-11-23 07:22:33,049 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5dfa0767 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:22:33, skipping insertion in model container [2018-11-23 07:22:33,049 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 07:22:32" (2/3) ... [2018-11-23 07:22:33,050 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5dfa0767 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 07:22:33, skipping insertion in model container [2018-11-23 07:22:33,050 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:22:33" (3/3) ... [2018-11-23 07:22:33,051 INFO L112 eAbstractionObserver]: Analyzing ICFG race-3_2-container_of-global_false-unreach-call.i [2018-11-23 07:22:33,081 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,082 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,085 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,085 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,085 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,086 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe Thread0_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,087 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,088 WARN L317 ript$VariableManager]: TermVariabe |Thread0_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,088 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,088 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,088 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,089 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,089 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,089 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,089 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,089 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,090 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~__mptr~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,090 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,090 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,090 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,090 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,091 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,091 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,091 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,091 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,091 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,092 WARN L317 ript$VariableManager]: TermVariabe Thread1_my_callback_~data~0.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,092 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,092 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,092 WARN L317 ript$VariableManager]: TermVariabe |Thread1_my_callback_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2018-11-23 07:22:33,125 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2018-11-23 07:22:33,125 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 07:22:33,132 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-11-23 07:22:33,146 INFO L257 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2018-11-23 07:22:33,169 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 07:22:33,169 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 07:22:33,169 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 07:22:33,169 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 07:22:33,169 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 07:22:33,169 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 07:22:33,169 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 07:22:33,170 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 07:22:33,178 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 137places, 145 transitions [2018-11-23 07:22:33,308 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 4725 states. [2018-11-23 07:22:33,311 INFO L276 IsEmpty]: Start isEmpty. Operand 4725 states. [2018-11-23 07:22:33,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-11-23 07:22:33,318 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:33,319 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:33,320 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:33,325 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:33,325 INFO L82 PathProgramCache]: Analyzing trace with hash 441784776, now seen corresponding path program 1 times [2018-11-23 07:22:33,327 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:33,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:33,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:33,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:33,415 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:33,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:33,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:33,648 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:33,648 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-23 07:22:33,648 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:33,651 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 07:22:33,659 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 07:22:33,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-11-23 07:22:33,661 INFO L87 Difference]: Start difference. First operand 4725 states. Second operand 6 states. [2018-11-23 07:22:34,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:34,050 INFO L93 Difference]: Finished difference Result 4724 states and 12876 transitions. [2018-11-23 07:22:34,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 07:22:34,052 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-11-23 07:22:34,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:34,079 INFO L225 Difference]: With dead ends: 4724 [2018-11-23 07:22:34,079 INFO L226 Difference]: Without dead ends: 3864 [2018-11-23 07:22:34,081 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2018-11-23 07:22:34,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3864 states. [2018-11-23 07:22:34,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3864 to 3863. [2018-11-23 07:22:34,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3863 states. [2018-11-23 07:22:34,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3863 states to 3863 states and 10474 transitions. [2018-11-23 07:22:34,227 INFO L78 Accepts]: Start accepts. Automaton has 3863 states and 10474 transitions. Word has length 31 [2018-11-23 07:22:34,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:34,228 INFO L480 AbstractCegarLoop]: Abstraction has 3863 states and 10474 transitions. [2018-11-23 07:22:34,228 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 07:22:34,228 INFO L276 IsEmpty]: Start isEmpty. Operand 3863 states and 10474 transitions. [2018-11-23 07:22:34,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-11-23 07:22:34,229 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:34,229 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:34,230 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:34,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:34,230 INFO L82 PathProgramCache]: Analyzing trace with hash -804856226, now seen corresponding path program 1 times [2018-11-23 07:22:34,230 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:34,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:34,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:34,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:34,244 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:34,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:34,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:34,443 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:34,443 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 07:22:34,443 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:34,445 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 07:22:34,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 07:22:34,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:22:34,446 INFO L87 Difference]: Start difference. First operand 3863 states and 10474 transitions. Second operand 8 states. [2018-11-23 07:22:34,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:34,901 INFO L93 Difference]: Finished difference Result 3865 states and 10476 transitions. [2018-11-23 07:22:34,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 07:22:34,902 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2018-11-23 07:22:34,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:34,911 INFO L225 Difference]: With dead ends: 3865 [2018-11-23 07:22:34,912 INFO L226 Difference]: Without dead ends: 3865 [2018-11-23 07:22:34,912 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=70, Invalid=140, Unknown=0, NotChecked=0, Total=210 [2018-11-23 07:22:34,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3865 states. [2018-11-23 07:22:34,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3865 to 3861. [2018-11-23 07:22:34,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3861 states. [2018-11-23 07:22:34,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3861 states to 3861 states and 10472 transitions. [2018-11-23 07:22:34,968 INFO L78 Accepts]: Start accepts. Automaton has 3861 states and 10472 transitions. Word has length 37 [2018-11-23 07:22:34,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:34,968 INFO L480 AbstractCegarLoop]: Abstraction has 3861 states and 10472 transitions. [2018-11-23 07:22:34,968 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 07:22:34,968 INFO L276 IsEmpty]: Start isEmpty. Operand 3861 states and 10472 transitions. [2018-11-23 07:22:34,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-11-23 07:22:34,970 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:34,970 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:34,970 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:34,971 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:34,971 INFO L82 PathProgramCache]: Analyzing trace with hash 1378309502, now seen corresponding path program 1 times [2018-11-23 07:22:34,971 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:34,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:34,977 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:34,977 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:34,977 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:34,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:35,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:35,109 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:35,109 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 07:22:35,110 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:35,110 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 07:22:35,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 07:22:35,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:22:35,110 INFO L87 Difference]: Start difference. First operand 3861 states and 10472 transitions. Second operand 8 states. [2018-11-23 07:22:35,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:35,920 INFO L93 Difference]: Finished difference Result 5825 states and 15810 transitions. [2018-11-23 07:22:35,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 07:22:35,920 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 55 [2018-11-23 07:22:35,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:35,934 INFO L225 Difference]: With dead ends: 5825 [2018-11-23 07:22:35,934 INFO L226 Difference]: Without dead ends: 5825 [2018-11-23 07:22:35,934 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=131, Invalid=289, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:22:35,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5825 states. [2018-11-23 07:22:35,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5825 to 4385. [2018-11-23 07:22:35,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4385 states. [2018-11-23 07:22:36,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4385 states to 4385 states and 11916 transitions. [2018-11-23 07:22:36,004 INFO L78 Accepts]: Start accepts. Automaton has 4385 states and 11916 transitions. Word has length 55 [2018-11-23 07:22:36,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:36,005 INFO L480 AbstractCegarLoop]: Abstraction has 4385 states and 11916 transitions. [2018-11-23 07:22:36,005 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 07:22:36,005 INFO L276 IsEmpty]: Start isEmpty. Operand 4385 states and 11916 transitions. [2018-11-23 07:22:36,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-11-23 07:22:36,008 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:36,008 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:36,009 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:36,010 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:36,010 INFO L82 PathProgramCache]: Analyzing trace with hash -1957942992, now seen corresponding path program 1 times [2018-11-23 07:22:36,010 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:36,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:36,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:36,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:36,016 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:36,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:36,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:36,143 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:36,143 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-11-23 07:22:36,143 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:36,143 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 07:22:36,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 07:22:36,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:22:36,144 INFO L87 Difference]: Start difference. First operand 4385 states and 11916 transitions. Second operand 8 states. [2018-11-23 07:22:36,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:36,742 INFO L93 Difference]: Finished difference Result 6349 states and 17158 transitions. [2018-11-23 07:22:36,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 07:22:36,743 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 61 [2018-11-23 07:22:36,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:36,756 INFO L225 Difference]: With dead ends: 6349 [2018-11-23 07:22:36,756 INFO L226 Difference]: Without dead ends: 5317 [2018-11-23 07:22:36,757 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=107, Invalid=235, Unknown=0, NotChecked=0, Total=342 [2018-11-23 07:22:36,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5317 states. [2018-11-23 07:22:36,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5317 to 5125. [2018-11-23 07:22:36,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5125 states. [2018-11-23 07:22:36,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5125 states to 5125 states and 13985 transitions. [2018-11-23 07:22:36,852 INFO L78 Accepts]: Start accepts. Automaton has 5125 states and 13985 transitions. Word has length 61 [2018-11-23 07:22:36,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:36,853 INFO L480 AbstractCegarLoop]: Abstraction has 5125 states and 13985 transitions. [2018-11-23 07:22:36,853 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 07:22:36,853 INFO L276 IsEmpty]: Start isEmpty. Operand 5125 states and 13985 transitions. [2018-11-23 07:22:36,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 07:22:36,857 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:36,857 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:36,858 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:36,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:36,858 INFO L82 PathProgramCache]: Analyzing trace with hash -1563836415, now seen corresponding path program 1 times [2018-11-23 07:22:36,858 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:36,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:36,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:36,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:36,867 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:36,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:36,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:36,937 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:36,937 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-23 07:22:36,937 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:36,937 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 07:22:36,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 07:22:36,938 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-23 07:22:36,938 INFO L87 Difference]: Start difference. First operand 5125 states and 13985 transitions. Second operand 5 states. [2018-11-23 07:22:36,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:36,997 INFO L93 Difference]: Finished difference Result 1780 states and 4650 transitions. [2018-11-23 07:22:36,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 07:22:36,997 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2018-11-23 07:22:36,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:37,001 INFO L225 Difference]: With dead ends: 1780 [2018-11-23 07:22:37,001 INFO L226 Difference]: Without dead ends: 1780 [2018-11-23 07:22:37,001 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-23 07:22:37,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1780 states. [2018-11-23 07:22:37,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1780 to 1780. [2018-11-23 07:22:37,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1780 states. [2018-11-23 07:22:37,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1780 states to 1780 states and 4650 transitions. [2018-11-23 07:22:37,029 INFO L78 Accepts]: Start accepts. Automaton has 1780 states and 4650 transitions. Word has length 67 [2018-11-23 07:22:37,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:37,030 INFO L480 AbstractCegarLoop]: Abstraction has 1780 states and 4650 transitions. [2018-11-23 07:22:37,030 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 07:22:37,030 INFO L276 IsEmpty]: Start isEmpty. Operand 1780 states and 4650 transitions. [2018-11-23 07:22:37,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:37,033 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:37,033 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:37,034 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:37,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:37,034 INFO L82 PathProgramCache]: Analyzing trace with hash -254166726, now seen corresponding path program 1 times [2018-11-23 07:22:37,034 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:37,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:37,041 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:37,041 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:37,041 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:37,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:37,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:37,877 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:37,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2018-11-23 07:22:37,877 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:37,877 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 07:22:37,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 07:22:37,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-11-23 07:22:37,878 INFO L87 Difference]: Start difference. First operand 1780 states and 4650 transitions. Second operand 18 states. [2018-11-23 07:22:38,730 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 36 [2018-11-23 07:22:38,868 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 40 [2018-11-23 07:22:39,017 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 45 [2018-11-23 07:22:40,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:40,029 INFO L93 Difference]: Finished difference Result 2172 states and 5448 transitions. [2018-11-23 07:22:40,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 07:22:40,030 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 96 [2018-11-23 07:22:40,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:40,034 INFO L225 Difference]: With dead ends: 2172 [2018-11-23 07:22:40,034 INFO L226 Difference]: Without dead ends: 2172 [2018-11-23 07:22:40,035 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 162 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=337, Invalid=923, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 07:22:40,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2172 states. [2018-11-23 07:22:40,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2172 to 1942. [2018-11-23 07:22:40,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1942 states. [2018-11-23 07:22:40,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1942 states to 1942 states and 4978 transitions. [2018-11-23 07:22:40,055 INFO L78 Accepts]: Start accepts. Automaton has 1942 states and 4978 transitions. Word has length 96 [2018-11-23 07:22:40,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:40,056 INFO L480 AbstractCegarLoop]: Abstraction has 1942 states and 4978 transitions. [2018-11-23 07:22:40,056 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 07:22:40,056 INFO L276 IsEmpty]: Start isEmpty. Operand 1942 states and 4978 transitions. [2018-11-23 07:22:40,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:40,059 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:40,059 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:40,059 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:40,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:40,059 INFO L82 PathProgramCache]: Analyzing trace with hash -536427754, now seen corresponding path program 2 times [2018-11-23 07:22:40,059 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:40,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:40,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:40,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:40,065 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:40,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:40,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:40,780 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:40,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2018-11-23 07:22:40,780 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:40,781 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 07:22:40,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 07:22:40,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-11-23 07:22:40,781 INFO L87 Difference]: Start difference. First operand 1942 states and 4978 transitions. Second operand 18 states. [2018-11-23 07:22:41,537 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:22:41,673 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 41 [2018-11-23 07:22:41,814 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 07:22:42,049 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 38 [2018-11-23 07:22:42,184 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 40 [2018-11-23 07:22:42,312 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 38 [2018-11-23 07:22:42,714 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 36 [2018-11-23 07:22:42,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:42,911 INFO L93 Difference]: Finished difference Result 2544 states and 6190 transitions. [2018-11-23 07:22:42,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-23 07:22:42,911 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 96 [2018-11-23 07:22:42,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:42,916 INFO L225 Difference]: With dead ends: 2544 [2018-11-23 07:22:42,916 INFO L226 Difference]: Without dead ends: 2544 [2018-11-23 07:22:42,916 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 156 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=348, Invalid=912, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 07:22:42,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2544 states. [2018-11-23 07:22:42,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2544 to 1915. [2018-11-23 07:22:42,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1915 states. [2018-11-23 07:22:42,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1915 states to 1915 states and 4915 transitions. [2018-11-23 07:22:42,948 INFO L78 Accepts]: Start accepts. Automaton has 1915 states and 4915 transitions. Word has length 96 [2018-11-23 07:22:42,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:42,948 INFO L480 AbstractCegarLoop]: Abstraction has 1915 states and 4915 transitions. [2018-11-23 07:22:42,948 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 07:22:42,948 INFO L276 IsEmpty]: Start isEmpty. Operand 1915 states and 4915 transitions. [2018-11-23 07:22:42,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:42,951 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:42,951 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:42,951 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:42,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:42,952 INFO L82 PathProgramCache]: Analyzing trace with hash -1768256902, now seen corresponding path program 3 times [2018-11-23 07:22:42,952 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:42,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:42,961 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:22:42,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:42,961 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:42,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:43,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:43,704 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:43,704 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2018-11-23 07:22:43,704 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:43,704 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 07:22:43,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 07:22:43,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-11-23 07:22:43,705 INFO L87 Difference]: Start difference. First operand 1915 states and 4915 transitions. Second operand 18 states. [2018-11-23 07:22:44,433 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 38 [2018-11-23 07:22:44,610 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 07:22:44,872 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 07:22:45,026 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 07:22:45,305 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 44 [2018-11-23 07:22:45,445 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:22:45,562 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 40 [2018-11-23 07:22:45,884 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 40 [2018-11-23 07:22:46,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:46,106 INFO L93 Difference]: Finished difference Result 2557 states and 6323 transitions. [2018-11-23 07:22:46,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-11-23 07:22:46,106 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 96 [2018-11-23 07:22:46,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:46,109 INFO L225 Difference]: With dead ends: 2557 [2018-11-23 07:22:46,109 INFO L226 Difference]: Without dead ends: 2557 [2018-11-23 07:22:46,110 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=359, Invalid=901, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 07:22:46,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2557 states. [2018-11-23 07:22:46,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2557 to 2152. [2018-11-23 07:22:46,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2152 states. [2018-11-23 07:22:46,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2152 states to 2152 states and 5534 transitions. [2018-11-23 07:22:46,149 INFO L78 Accepts]: Start accepts. Automaton has 2152 states and 5534 transitions. Word has length 96 [2018-11-23 07:22:46,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:46,149 INFO L480 AbstractCegarLoop]: Abstraction has 2152 states and 5534 transitions. [2018-11-23 07:22:46,149 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 07:22:46,149 INFO L276 IsEmpty]: Start isEmpty. Operand 2152 states and 5534 transitions. [2018-11-23 07:22:46,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:46,153 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:46,153 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:46,154 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:46,154 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:46,154 INFO L82 PathProgramCache]: Analyzing trace with hash 585794838, now seen corresponding path program 4 times [2018-11-23 07:22:46,154 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:46,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:46,163 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:22:46,163 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:46,163 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:46,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:47,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:47,238 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:47,238 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:22:47,238 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:47,238 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:22:47,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:22:47,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:22:47,239 INFO L87 Difference]: Start difference. First operand 2152 states and 5534 transitions. Second operand 21 states. [2018-11-23 07:22:47,862 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:22:48,002 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:22:48,176 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 07:22:48,523 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 07:22:48,679 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 46 [2018-11-23 07:22:48,881 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 07:22:49,052 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 07:22:49,258 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:22:49,465 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 07:22:49,795 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 07:22:49,963 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:22:50,094 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 07:22:50,449 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:22:50,693 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 45 [2018-11-23 07:22:50,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:50,709 INFO L93 Difference]: Finished difference Result 3287 states and 7934 transitions. [2018-11-23 07:22:50,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 07:22:50,709 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:22:50,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:50,714 INFO L225 Difference]: With dead ends: 3287 [2018-11-23 07:22:50,714 INFO L226 Difference]: Without dead ends: 3287 [2018-11-23 07:22:50,714 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=486, Invalid=1320, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:22:50,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3287 states. [2018-11-23 07:22:50,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3287 to 2329. [2018-11-23 07:22:50,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2329 states. [2018-11-23 07:22:50,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2329 states to 2329 states and 5985 transitions. [2018-11-23 07:22:50,753 INFO L78 Accepts]: Start accepts. Automaton has 2329 states and 5985 transitions. Word has length 96 [2018-11-23 07:22:50,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:50,754 INFO L480 AbstractCegarLoop]: Abstraction has 2329 states and 5985 transitions. [2018-11-23 07:22:50,754 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:22:50,754 INFO L276 IsEmpty]: Start isEmpty. Operand 2329 states and 5985 transitions. [2018-11-23 07:22:50,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:50,758 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:50,758 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:50,758 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:50,758 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:50,758 INFO L82 PathProgramCache]: Analyzing trace with hash 832286298, now seen corresponding path program 5 times [2018-11-23 07:22:50,758 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:50,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:50,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:22:50,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:50,765 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:50,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:51,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:51,866 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:51,866 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:22:51,866 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:51,867 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:22:51,867 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:22:51,867 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:22:51,867 INFO L87 Difference]: Start difference. First operand 2329 states and 5985 transitions. Second operand 21 states. [2018-11-23 07:22:52,533 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:22:52,672 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:22:52,826 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 07:22:53,062 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 07:22:53,241 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:22:53,600 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 07:22:53,833 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 07:22:54,009 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 07:22:54,213 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:22:54,421 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 07:22:54,813 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:22:54,970 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 07:22:55,149 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 48 [2018-11-23 07:22:55,327 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:22:55,475 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 07:22:55,701 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 07:22:56,003 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 07:22:56,146 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:22:56,487 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 49 [2018-11-23 07:22:56,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:22:56,608 INFO L93 Difference]: Finished difference Result 5310 states and 12783 transitions. [2018-11-23 07:22:56,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-23 07:22:56,608 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:22:56,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:22:56,615 INFO L225 Difference]: With dead ends: 5310 [2018-11-23 07:22:56,616 INFO L226 Difference]: Without dead ends: 5310 [2018-11-23 07:22:56,616 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 401 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=665, Invalid=1785, Unknown=0, NotChecked=0, Total=2450 [2018-11-23 07:22:56,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5310 states. [2018-11-23 07:22:56,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5310 to 2362. [2018-11-23 07:22:56,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2362 states. [2018-11-23 07:22:56,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2362 states to 2362 states and 6084 transitions. [2018-11-23 07:22:56,661 INFO L78 Accepts]: Start accepts. Automaton has 2362 states and 6084 transitions. Word has length 96 [2018-11-23 07:22:56,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:22:56,661 INFO L480 AbstractCegarLoop]: Abstraction has 2362 states and 6084 transitions. [2018-11-23 07:22:56,661 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:22:56,661 INFO L276 IsEmpty]: Start isEmpty. Operand 2362 states and 6084 transitions. [2018-11-23 07:22:56,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:22:56,665 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:22:56,665 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:22:56,665 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:22:56,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:22:56,666 INFO L82 PathProgramCache]: Analyzing trace with hash -417730346, now seen corresponding path program 6 times [2018-11-23 07:22:56,666 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:22:56,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:56,673 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:22:56,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:22:56,673 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:22:56,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:22:57,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:22:57,672 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:22:57,672 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:22:57,672 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:22:57,673 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:22:57,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:22:57,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:22:57,673 INFO L87 Difference]: Start difference. First operand 2362 states and 6084 transitions. Second operand 21 states. [2018-11-23 07:22:58,215 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 30 [2018-11-23 07:22:58,378 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:22:58,526 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:22:58,696 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 07:22:58,921 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 07:22:59,095 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:22:59,311 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 07:22:59,566 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:22:59,891 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 07:23:00,121 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:23:00,308 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 51 [2018-11-23 07:23:00,513 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 61 [2018-11-23 07:23:00,912 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 54 [2018-11-23 07:23:01,071 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 07:23:01,258 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 52 [2018-11-23 07:23:01,410 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:23:01,570 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 07:23:01,698 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 07:23:01,893 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 50 [2018-11-23 07:23:02,057 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:23:02,415 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:23:02,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:02,535 INFO L93 Difference]: Finished difference Result 4637 states and 11344 transitions. [2018-11-23 07:23:02,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 07:23:02,536 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:02,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:02,538 INFO L225 Difference]: With dead ends: 4637 [2018-11-23 07:23:02,538 INFO L226 Difference]: Without dead ends: 4637 [2018-11-23 07:23:02,539 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 344 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=651, Invalid=1701, Unknown=0, NotChecked=0, Total=2352 [2018-11-23 07:23:02,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4637 states. [2018-11-23 07:23:02,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4637 to 2461. [2018-11-23 07:23:02,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2461 states. [2018-11-23 07:23:02,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2461 states to 2461 states and 6381 transitions. [2018-11-23 07:23:02,571 INFO L78 Accepts]: Start accepts. Automaton has 2461 states and 6381 transitions. Word has length 96 [2018-11-23 07:23:02,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:02,572 INFO L480 AbstractCegarLoop]: Abstraction has 2461 states and 6381 transitions. [2018-11-23 07:23:02,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:02,572 INFO L276 IsEmpty]: Start isEmpty. Operand 2461 states and 6381 transitions. [2018-11-23 07:23:02,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:02,575 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:02,576 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:02,576 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:02,576 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:02,576 INFO L82 PathProgramCache]: Analyzing trace with hash -569868994, now seen corresponding path program 7 times [2018-11-23 07:23:02,576 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:02,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:02,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:02,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:02,581 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:02,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:03,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:03,517 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:03,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:03,517 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:03,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:03,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:03,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:03,518 INFO L87 Difference]: Start difference. First operand 2461 states and 6381 transitions. Second operand 21 states. [2018-11-23 07:23:04,219 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:04,465 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:23:04,613 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 07:23:04,779 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 46 [2018-11-23 07:23:04,979 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 07:23:05,166 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 07:23:05,356 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:23:05,593 WARN L180 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 07:23:05,911 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:23:06,058 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:23:06,204 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:06,654 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:23:06,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:06,898 INFO L93 Difference]: Finished difference Result 3589 states and 8624 transitions. [2018-11-23 07:23:06,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 07:23:06,898 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:06,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:06,901 INFO L225 Difference]: With dead ends: 3589 [2018-11-23 07:23:06,901 INFO L226 Difference]: Without dead ends: 3589 [2018-11-23 07:23:06,901 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=474, Invalid=1332, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:23:06,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3589 states. [2018-11-23 07:23:06,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3589 to 2488. [2018-11-23 07:23:06,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2488 states. [2018-11-23 07:23:06,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2488 states to 2488 states and 6444 transitions. [2018-11-23 07:23:06,926 INFO L78 Accepts]: Start accepts. Automaton has 2488 states and 6444 transitions. Word has length 96 [2018-11-23 07:23:06,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:06,927 INFO L480 AbstractCegarLoop]: Abstraction has 2488 states and 6444 transitions. [2018-11-23 07:23:06,927 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:06,927 INFO L276 IsEmpty]: Start isEmpty. Operand 2488 states and 6444 transitions. [2018-11-23 07:23:06,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:06,929 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:06,929 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:06,929 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:06,930 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:06,930 INFO L82 PathProgramCache]: Analyzing trace with hash -252325186, now seen corresponding path program 8 times [2018-11-23 07:23:06,930 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:06,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:06,935 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:23:06,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:06,935 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:06,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:07,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:07,849 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:07,849 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:07,849 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:07,849 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:07,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:07,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:07,849 INFO L87 Difference]: Start difference. First operand 2488 states and 6444 transitions. Second operand 21 states. [2018-11-23 07:23:08,520 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:08,764 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:23:08,938 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:23:09,113 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 07:23:09,319 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:23:09,509 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 51 [2018-11-23 07:23:09,721 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 61 [2018-11-23 07:23:10,037 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:23:10,185 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:23:10,332 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:10,808 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:23:11,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:11,059 INFO L93 Difference]: Finished difference Result 3752 states and 8953 transitions. [2018-11-23 07:23:11,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:11,059 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:11,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:11,062 INFO L225 Difference]: With dead ends: 3752 [2018-11-23 07:23:11,062 INFO L226 Difference]: Without dead ends: 3752 [2018-11-23 07:23:11,062 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 230 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=444, Invalid=1278, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:11,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3752 states. [2018-11-23 07:23:11,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3752 to 2490. [2018-11-23 07:23:11,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2490 states. [2018-11-23 07:23:11,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2490 states to 2490 states and 6449 transitions. [2018-11-23 07:23:11,093 INFO L78 Accepts]: Start accepts. Automaton has 2490 states and 6449 transitions. Word has length 96 [2018-11-23 07:23:11,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:11,093 INFO L480 AbstractCegarLoop]: Abstraction has 2490 states and 6449 transitions. [2018-11-23 07:23:11,094 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:11,094 INFO L276 IsEmpty]: Start isEmpty. Operand 2490 states and 6449 transitions. [2018-11-23 07:23:11,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:11,096 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:11,097 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:11,097 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:11,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:11,097 INFO L82 PathProgramCache]: Analyzing trace with hash 294181424, now seen corresponding path program 9 times [2018-11-23 07:23:11,097 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:11,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:11,103 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:11,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:11,103 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:11,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:11,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:11,997 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:11,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:11,997 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:11,997 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:11,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:11,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:11,997 INFO L87 Difference]: Start difference. First operand 2490 states and 6449 transitions. Second operand 21 states. [2018-11-23 07:23:12,641 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:12,885 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:23:13,054 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 07:23:13,265 WARN L180 SmtUtils]: Spent 174.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:23:13,465 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:23:13,655 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:23:13,870 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 07:23:14,184 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:23:14,327 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:23:14,470 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:14,906 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:23:15,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:15,121 INFO L93 Difference]: Finished difference Result 3457 states and 8359 transitions. [2018-11-23 07:23:15,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:15,122 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:15,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:15,124 INFO L225 Difference]: With dead ends: 3457 [2018-11-23 07:23:15,124 INFO L226 Difference]: Without dead ends: 3457 [2018-11-23 07:23:15,124 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=445, Invalid=1277, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:15,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3457 states. [2018-11-23 07:23:15,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3457 to 2496. [2018-11-23 07:23:15,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2496 states. [2018-11-23 07:23:15,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2496 states to 2496 states and 6464 transitions. [2018-11-23 07:23:15,147 INFO L78 Accepts]: Start accepts. Automaton has 2496 states and 6464 transitions. Word has length 96 [2018-11-23 07:23:15,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:15,148 INFO L480 AbstractCegarLoop]: Abstraction has 2496 states and 6464 transitions. [2018-11-23 07:23:15,148 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:15,148 INFO L276 IsEmpty]: Start isEmpty. Operand 2496 states and 6464 transitions. [2018-11-23 07:23:15,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:15,150 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:15,150 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:15,150 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:15,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:15,151 INFO L82 PathProgramCache]: Analyzing trace with hash 1256625598, now seen corresponding path program 10 times [2018-11-23 07:23:15,151 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:15,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:15,154 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:15,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:15,154 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:15,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:16,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:16,036 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:16,036 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:16,037 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:16,037 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:16,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:16,037 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:16,037 INFO L87 Difference]: Start difference. First operand 2496 states and 6464 transitions. Second operand 21 states. [2018-11-23 07:23:16,672 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:16,859 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:17,021 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:23:17,227 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-23 07:23:17,544 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:23:17,722 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 51 [2018-11-23 07:23:17,912 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:23:18,124 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 07:23:18,489 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:23:18,665 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:23:18,818 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-23 07:23:19,068 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 07:23:19,251 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 07:23:19,514 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 50 [2018-11-23 07:23:19,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:19,525 INFO L93 Difference]: Finished difference Result 5854 states and 14349 transitions. [2018-11-23 07:23:19,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:19,525 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:19,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:19,529 INFO L225 Difference]: With dead ends: 5854 [2018-11-23 07:23:19,529 INFO L226 Difference]: Without dead ends: 5854 [2018-11-23 07:23:19,529 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=466, Invalid=1256, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:19,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5854 states. [2018-11-23 07:23:19,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5854 to 2540. [2018-11-23 07:23:19,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 07:23:19,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 07:23:19,570 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 07:23:19,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:19,570 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 07:23:19,570 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:19,571 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 07:23:19,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:19,574 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:19,574 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:19,574 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:19,574 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:19,574 INFO L82 PathProgramCache]: Analyzing trace with hash 6608954, now seen corresponding path program 11 times [2018-11-23 07:23:19,574 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:19,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:19,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:23:19,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:19,579 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:19,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:20,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:20,446 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:20,446 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:20,446 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:20,446 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:20,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:20,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:20,447 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 07:23:21,100 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:21,303 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:21,468 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 07:23:21,658 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-23 07:23:21,830 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 48 [2018-11-23 07:23:22,035 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 52 [2018-11-23 07:23:22,391 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 07:23:22,573 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 07:23:22,786 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 61 [2018-11-23 07:23:23,179 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 54 [2018-11-23 07:23:23,348 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 07:23:23,543 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 52 [2018-11-23 07:23:23,712 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 07:23:23,875 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 50 [2018-11-23 07:23:24,023 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 47 [2018-11-23 07:23:24,217 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 50 [2018-11-23 07:23:24,377 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 07:23:24,756 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 07:23:24,880 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 07:23:24,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:24,888 INFO L93 Difference]: Finished difference Result 6960 states and 17185 transitions. [2018-11-23 07:23:24,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 07:23:24,888 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:24,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:24,892 INFO L225 Difference]: With dead ends: 6960 [2018-11-23 07:23:24,892 INFO L226 Difference]: Without dead ends: 6960 [2018-11-23 07:23:24,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 292 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=604, Invalid=1558, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 07:23:24,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6960 states. [2018-11-23 07:23:24,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6960 to 2507. [2018-11-23 07:23:24,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2507 states. [2018-11-23 07:23:24,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2507 states to 2507 states and 6497 transitions. [2018-11-23 07:23:24,924 INFO L78 Accepts]: Start accepts. Automaton has 2507 states and 6497 transitions. Word has length 96 [2018-11-23 07:23:24,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:24,925 INFO L480 AbstractCegarLoop]: Abstraction has 2507 states and 6497 transitions. [2018-11-23 07:23:24,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:24,925 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 6497 transitions. [2018-11-23 07:23:24,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:24,927 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:24,927 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:24,928 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:24,928 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:24,928 INFO L82 PathProgramCache]: Analyzing trace with hash -795853046, now seen corresponding path program 12 times [2018-11-23 07:23:24,928 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:24,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:24,931 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:24,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:24,931 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:24,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:25,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:25,820 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:25,820 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:25,820 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:25,820 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:25,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:25,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:25,821 INFO L87 Difference]: Start difference. First operand 2507 states and 6497 transitions. Second operand 21 states. [2018-11-23 07:23:26,504 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:26,686 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:23:26,933 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:23:27,103 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 47 [2018-11-23 07:23:27,287 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 51 [2018-11-23 07:23:27,473 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 51 [2018-11-23 07:23:27,683 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 07:23:28,012 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 43 [2018-11-23 07:23:28,200 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 45 [2018-11-23 07:23:28,364 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 44 [2018-11-23 07:23:28,595 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 07:23:28,886 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 42 [2018-11-23 07:23:29,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:29,161 INFO L93 Difference]: Finished difference Result 4983 states and 12154 transitions. [2018-11-23 07:23:29,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:29,162 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:29,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:29,165 INFO L225 Difference]: With dead ends: 4983 [2018-11-23 07:23:29,165 INFO L226 Difference]: Without dead ends: 4983 [2018-11-23 07:23:29,165 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=455, Invalid=1267, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:29,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4983 states. [2018-11-23 07:23:29,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4983 to 2509. [2018-11-23 07:23:29,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2509 states. [2018-11-23 07:23:29,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2509 states to 2509 states and 6502 transitions. [2018-11-23 07:23:29,196 INFO L78 Accepts]: Start accepts. Automaton has 2509 states and 6502 transitions. Word has length 96 [2018-11-23 07:23:29,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:29,196 INFO L480 AbstractCegarLoop]: Abstraction has 2509 states and 6502 transitions. [2018-11-23 07:23:29,196 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:29,196 INFO L276 IsEmpty]: Start isEmpty. Operand 2509 states and 6502 transitions. [2018-11-23 07:23:29,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:29,198 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:29,198 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:29,199 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:29,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:29,199 INFO L82 PathProgramCache]: Analyzing trace with hash -872809876, now seen corresponding path program 13 times [2018-11-23 07:23:29,199 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:29,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:29,203 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:29,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:29,203 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:29,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:30,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:30,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:30,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:30,111 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:30,111 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:30,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:30,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:30,111 INFO L87 Difference]: Start difference. First operand 2509 states and 6502 transitions. Second operand 21 states. [2018-11-23 07:23:30,630 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 30 [2018-11-23 07:23:30,765 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:30,946 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 07:23:31,187 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 07:23:31,374 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:23:31,572 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:23:31,783 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:23:31,996 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 07:23:32,349 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 43 [2018-11-23 07:23:32,525 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 45 [2018-11-23 07:23:32,687 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 07:23:32,824 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 42 [2018-11-23 07:23:33,194 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 42 [2018-11-23 07:23:33,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:33,448 INFO L93 Difference]: Finished difference Result 4880 states and 11957 transitions. [2018-11-23 07:23:33,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:33,448 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:33,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:33,451 INFO L225 Difference]: With dead ends: 4880 [2018-11-23 07:23:33,451 INFO L226 Difference]: Without dead ends: 4880 [2018-11-23 07:23:33,452 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=456, Invalid=1266, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:33,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4880 states. [2018-11-23 07:23:33,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4880 to 2507. [2018-11-23 07:23:33,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2507 states. [2018-11-23 07:23:33,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2507 states to 2507 states and 6497 transitions. [2018-11-23 07:23:33,478 INFO L78 Accepts]: Start accepts. Automaton has 2507 states and 6497 transitions. Word has length 96 [2018-11-23 07:23:33,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:33,479 INFO L480 AbstractCegarLoop]: Abstraction has 2507 states and 6497 transitions. [2018-11-23 07:23:33,479 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:33,479 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 6497 transitions. [2018-11-23 07:23:33,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:33,481 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:33,481 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:33,482 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:33,482 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:33,482 INFO L82 PathProgramCache]: Analyzing trace with hash 1213451052, now seen corresponding path program 14 times [2018-11-23 07:23:33,482 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:33,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:33,487 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:23:33,487 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:33,487 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:33,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:34,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:34,402 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:34,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:34,402 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:34,402 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:34,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:34,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:34,402 INFO L87 Difference]: Start difference. First operand 2507 states and 6497 transitions. Second operand 21 states. [2018-11-23 07:23:35,048 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:35,242 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 07:23:35,417 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 43 [2018-11-23 07:23:35,614 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:23:35,796 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:23:36,012 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 54 [2018-11-23 07:23:36,407 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:23:36,595 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:23:36,809 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 62 [2018-11-23 07:23:37,218 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 52 [2018-11-23 07:23:37,421 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 56 [2018-11-23 07:23:37,609 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 07:23:37,810 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 54 [2018-11-23 07:23:37,974 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 07:23:38,155 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 52 [2018-11-23 07:23:38,357 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:23:38,550 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:23:38,807 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 51 [2018-11-23 07:23:38,937 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:23:39,079 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 55 [2018-11-23 07:23:39,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:39,103 INFO L93 Difference]: Finished difference Result 5593 states and 13805 transitions. [2018-11-23 07:23:39,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 07:23:39,103 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:39,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:39,106 INFO L225 Difference]: With dead ends: 5593 [2018-11-23 07:23:39,107 INFO L226 Difference]: Without dead ends: 5593 [2018-11-23 07:23:39,107 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=605, Invalid=1557, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 07:23:39,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5593 states. [2018-11-23 07:23:39,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5593 to 2540. [2018-11-23 07:23:39,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 07:23:39,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 07:23:39,136 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 07:23:39,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:39,136 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 07:23:39,136 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:39,136 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 07:23:39,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:39,138 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:39,138 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:39,138 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:39,139 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:39,139 INFO L82 PathProgramCache]: Analyzing trace with hash 1701431392, now seen corresponding path program 15 times [2018-11-23 07:23:39,139 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:39,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:39,141 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:39,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:39,142 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:39,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:40,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:40,011 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:40,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:40,011 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:40,012 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:40,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:40,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:40,012 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 07:23:40,701 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:23:40,915 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 07:23:41,096 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 43 [2018-11-23 07:23:41,305 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:23:41,698 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 49 [2018-11-23 07:23:41,901 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 53 [2018-11-23 07:23:42,093 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 53 [2018-11-23 07:23:42,317 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 62 [2018-11-23 07:23:42,757 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 52 [2018-11-23 07:23:42,948 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 07:23:43,113 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 07:23:43,530 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:23:43,800 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:23:43,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:43,812 INFO L93 Difference]: Finished difference Result 4425 states and 10876 transitions. [2018-11-23 07:23:43,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:23:43,813 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:43,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:43,814 INFO L225 Difference]: With dead ends: 4425 [2018-11-23 07:23:43,814 INFO L226 Difference]: Without dead ends: 4425 [2018-11-23 07:23:43,815 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=467, Invalid=1255, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:43,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4425 states. [2018-11-23 07:23:43,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4425 to 2540. [2018-11-23 07:23:43,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2540 states. [2018-11-23 07:23:43,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 6596 transitions. [2018-11-23 07:23:43,836 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 6596 transitions. Word has length 96 [2018-11-23 07:23:43,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:43,837 INFO L480 AbstractCegarLoop]: Abstraction has 2540 states and 6596 transitions. [2018-11-23 07:23:43,837 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:43,837 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 6596 transitions. [2018-11-23 07:23:43,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:43,838 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:43,839 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:43,839 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:43,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:43,839 INFO L82 PathProgramCache]: Analyzing trace with hash 1195653978, now seen corresponding path program 16 times [2018-11-23 07:23:43,839 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:43,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:43,842 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:43,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:43,842 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:43,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:44,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:44,691 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:44,691 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:44,691 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:44,691 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:44,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:44,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:44,691 INFO L87 Difference]: Start difference. First operand 2540 states and 6596 transitions. Second operand 21 states. [2018-11-23 07:23:45,529 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:23:45,687 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 07:23:45,856 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 46 [2018-11-23 07:23:46,059 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 07:23:46,247 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 07:23:46,444 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:23:46,665 WARN L180 SmtUtils]: Spent 182.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 61 [2018-11-23 07:23:47,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:47,789 INFO L93 Difference]: Finished difference Result 3269 states and 8034 transitions. [2018-11-23 07:23:47,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 07:23:47,790 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:47,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:47,791 INFO L225 Difference]: With dead ends: 3269 [2018-11-23 07:23:47,791 INFO L226 Difference]: Without dead ends: 3269 [2018-11-23 07:23:47,792 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=464, Invalid=1342, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:23:47,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3269 states. [2018-11-23 07:23:47,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3269 to 2480. [2018-11-23 07:23:47,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2480 states. [2018-11-23 07:23:47,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2480 states to 2480 states and 6455 transitions. [2018-11-23 07:23:47,812 INFO L78 Accepts]: Start accepts. Automaton has 2480 states and 6455 transitions. Word has length 96 [2018-11-23 07:23:47,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:47,812 INFO L480 AbstractCegarLoop]: Abstraction has 2480 states and 6455 transitions. [2018-11-23 07:23:47,812 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:47,812 INFO L276 IsEmpty]: Start isEmpty. Operand 2480 states and 6455 transitions. [2018-11-23 07:23:47,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:47,814 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:47,814 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:47,814 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:47,814 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:47,814 INFO L82 PathProgramCache]: Analyzing trace with hash 1513197786, now seen corresponding path program 17 times [2018-11-23 07:23:47,814 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:47,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:47,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:23:47,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:47,817 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:47,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:49,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:49,052 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:49,052 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:49,052 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:49,052 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:49,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:49,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:49,053 INFO L87 Difference]: Start difference. First operand 2480 states and 6455 transitions. Second operand 21 states. [2018-11-23 07:23:49,847 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:23:50,037 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:23:50,216 WARN L180 SmtUtils]: Spent 148.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 07:23:50,410 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:23:50,604 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 51 [2018-11-23 07:23:50,829 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 61 [2018-11-23 07:23:51,375 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 45 DAG size of output: 34 [2018-11-23 07:23:51,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:51,950 INFO L93 Difference]: Finished difference Result 3810 states and 9142 transitions. [2018-11-23 07:23:51,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 07:23:51,950 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:51,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:51,952 INFO L225 Difference]: With dead ends: 3810 [2018-11-23 07:23:51,952 INFO L226 Difference]: Without dead ends: 3810 [2018-11-23 07:23:51,953 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=433, Invalid=1289, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:51,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3810 states. [2018-11-23 07:23:51,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3810 to 2482. [2018-11-23 07:23:51,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2482 states. [2018-11-23 07:23:51,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2482 states to 2482 states and 6460 transitions. [2018-11-23 07:23:51,974 INFO L78 Accepts]: Start accepts. Automaton has 2482 states and 6460 transitions. Word has length 96 [2018-11-23 07:23:51,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:51,974 INFO L480 AbstractCegarLoop]: Abstraction has 2482 states and 6460 transitions. [2018-11-23 07:23:51,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:51,974 INFO L276 IsEmpty]: Start isEmpty. Operand 2482 states and 6460 transitions. [2018-11-23 07:23:51,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:51,976 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:51,976 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:51,976 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:51,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:51,976 INFO L82 PathProgramCache]: Analyzing trace with hash 2059704396, now seen corresponding path program 18 times [2018-11-23 07:23:51,976 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:51,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:51,979 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:51,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:51,979 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:51,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:52,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:52,918 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:52,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:52,918 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:52,918 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:52,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:52,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:52,919 INFO L87 Difference]: Start difference. First operand 2482 states and 6460 transitions. Second operand 21 states. [2018-11-23 07:23:53,733 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 07:23:53,921 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:23:54,108 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 07:23:54,308 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:23:54,492 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:23:54,700 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 61 [2018-11-23 07:23:55,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:55,832 INFO L93 Difference]: Finished difference Result 3515 states and 8548 transitions. [2018-11-23 07:23:55,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 07:23:55,833 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:55,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:55,834 INFO L225 Difference]: With dead ends: 3515 [2018-11-23 07:23:55,834 INFO L226 Difference]: Without dead ends: 3515 [2018-11-23 07:23:55,835 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=434, Invalid=1288, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:55,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3515 states. [2018-11-23 07:23:55,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3515 to 2474. [2018-11-23 07:23:55,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2018-11-23 07:23:55,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 6440 transitions. [2018-11-23 07:23:55,855 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 6440 transitions. Word has length 96 [2018-11-23 07:23:55,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:55,855 INFO L480 AbstractCegarLoop]: Abstraction has 2474 states and 6440 transitions. [2018-11-23 07:23:55,855 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:55,856 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 6440 transitions. [2018-11-23 07:23:55,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:55,857 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:55,857 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:55,858 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:55,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:55,858 INFO L82 PathProgramCache]: Analyzing trace with hash -1718963238, now seen corresponding path program 19 times [2018-11-23 07:23:55,858 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:55,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:55,861 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:23:55,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:55,861 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:55,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:23:56,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:23:56,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:23:56,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:23:56,846 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:23:56,846 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:23:56,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:23:56,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:23:56,847 INFO L87 Difference]: Start difference. First operand 2474 states and 6440 transitions. Second operand 21 states. [2018-11-23 07:23:57,699 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 36 [2018-11-23 07:23:57,875 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 41 [2018-11-23 07:23:58,048 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 46 [2018-11-23 07:23:58,240 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:23:58,424 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 51 [2018-11-23 07:23:58,640 WARN L180 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 61 [2018-11-23 07:23:59,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:23:59,796 INFO L93 Difference]: Finished difference Result 3489 states and 8492 transitions. [2018-11-23 07:23:59,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 07:23:59,796 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:23:59,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:23:59,798 INFO L225 Difference]: With dead ends: 3489 [2018-11-23 07:23:59,798 INFO L226 Difference]: Without dead ends: 3489 [2018-11-23 07:23:59,798 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=433, Invalid=1289, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:23:59,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3489 states. [2018-11-23 07:23:59,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3489 to 2482. [2018-11-23 07:23:59,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2482 states. [2018-11-23 07:23:59,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2482 states to 2482 states and 6460 transitions. [2018-11-23 07:23:59,818 INFO L78 Accepts]: Start accepts. Automaton has 2482 states and 6460 transitions. Word has length 96 [2018-11-23 07:23:59,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:23:59,818 INFO L480 AbstractCegarLoop]: Abstraction has 2482 states and 6460 transitions. [2018-11-23 07:23:59,818 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:23:59,818 INFO L276 IsEmpty]: Start isEmpty. Operand 2482 states and 6460 transitions. [2018-11-23 07:23:59,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:23:59,820 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:23:59,820 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:23:59,820 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:23:59,820 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:23:59,821 INFO L82 PathProgramCache]: Analyzing trace with hash -1172456628, now seen corresponding path program 20 times [2018-11-23 07:23:59,821 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:23:59,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:59,824 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:23:59,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:23:59,824 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:23:59,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:00,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:00,688 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:00,688 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:00,688 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:00,689 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:00,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:00,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:00,689 INFO L87 Difference]: Start difference. First operand 2482 states and 6460 transitions. Second operand 21 states. [2018-11-23 07:24:01,571 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 07:24:01,747 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 41 [2018-11-23 07:24:01,943 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 48 [2018-11-23 07:24:02,145 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:24:02,333 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:24:02,546 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 61 [2018-11-23 07:24:03,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:03,721 INFO L93 Difference]: Finished difference Result 3707 states and 8945 transitions. [2018-11-23 07:24:03,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 07:24:03,721 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:03,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:03,723 INFO L225 Difference]: With dead ends: 3707 [2018-11-23 07:24:03,723 INFO L226 Difference]: Without dead ends: 3707 [2018-11-23 07:24:03,723 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=434, Invalid=1288, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:03,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3707 states. [2018-11-23 07:24:03,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3707 to 2480. [2018-11-23 07:24:03,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2480 states. [2018-11-23 07:24:03,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2480 states to 2480 states and 6455 transitions. [2018-11-23 07:24:03,746 INFO L78 Accepts]: Start accepts. Automaton has 2480 states and 6455 transitions. Word has length 96 [2018-11-23 07:24:03,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:03,746 INFO L480 AbstractCegarLoop]: Abstraction has 2480 states and 6455 transitions. [2018-11-23 07:24:03,746 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:03,747 INFO L276 IsEmpty]: Start isEmpty. Operand 2480 states and 6455 transitions. [2018-11-23 07:24:03,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:03,748 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:03,748 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:03,749 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:03,749 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:03,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1372594410, now seen corresponding path program 21 times [2018-11-23 07:24:03,749 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:03,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:03,752 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:03,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:03,753 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:03,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:04,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:04,729 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:04,729 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:04,729 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:04,729 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:04,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:04,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:04,730 INFO L87 Difference]: Start difference. First operand 2480 states and 6455 transitions. Second operand 21 states. [2018-11-23 07:24:05,572 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 07:24:05,732 WARN L180 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 42 [2018-11-23 07:24:05,905 WARN L180 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 46 [2018-11-23 07:24:06,119 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:24:06,333 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:24:06,525 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:24:06,749 WARN L180 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 62 [2018-11-23 07:24:07,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:07,856 INFO L93 Difference]: Finished difference Result 3192 states and 7893 transitions. [2018-11-23 07:24:07,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-11-23 07:24:07,856 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:07,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:07,858 INFO L225 Difference]: With dead ends: 3192 [2018-11-23 07:24:07,858 INFO L226 Difference]: Without dead ends: 3192 [2018-11-23 07:24:07,858 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=466, Invalid=1340, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:24:07,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3192 states. [2018-11-23 07:24:07,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3192 to 2498. [2018-11-23 07:24:07,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2498 states. [2018-11-23 07:24:07,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2498 states to 2498 states and 6500 transitions. [2018-11-23 07:24:07,876 INFO L78 Accepts]: Start accepts. Automaton has 2498 states and 6500 transitions. Word has length 96 [2018-11-23 07:24:07,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:07,876 INFO L480 AbstractCegarLoop]: Abstraction has 2498 states and 6500 transitions. [2018-11-23 07:24:07,876 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:07,876 INFO L276 IsEmpty]: Start isEmpty. Operand 2498 states and 6500 transitions. [2018-11-23 07:24:07,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:07,878 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:07,878 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:07,878 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:07,878 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:07,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1976775582, now seen corresponding path program 22 times [2018-11-23 07:24:07,878 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:07,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:07,881 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:07,881 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:07,882 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:07,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:08,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:08,725 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:08,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:08,725 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:08,725 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:08,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:08,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:08,725 INFO L87 Difference]: Start difference. First operand 2498 states and 6500 transitions. Second operand 21 states. [2018-11-23 07:24:09,402 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:09,567 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:24:09,731 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 44 [2018-11-23 07:24:09,917 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 48 [2018-11-23 07:24:10,255 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 47 [2018-11-23 07:24:10,430 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 51 [2018-11-23 07:24:10,644 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:24:10,861 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 62 [2018-11-23 07:24:11,240 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 07:24:11,425 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:24:11,575 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 47 [2018-11-23 07:24:11,975 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:24:12,234 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 50 [2018-11-23 07:24:12,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:12,245 INFO L93 Difference]: Finished difference Result 4235 states and 10394 transitions. [2018-11-23 07:24:12,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:12,245 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:12,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:12,247 INFO L225 Difference]: With dead ends: 4235 [2018-11-23 07:24:12,247 INFO L226 Difference]: Without dead ends: 4235 [2018-11-23 07:24:12,247 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=466, Invalid=1256, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:12,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4235 states. [2018-11-23 07:24:12,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4235 to 2498. [2018-11-23 07:24:12,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2498 states. [2018-11-23 07:24:12,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2498 states to 2498 states and 6500 transitions. [2018-11-23 07:24:12,268 INFO L78 Accepts]: Start accepts. Automaton has 2498 states and 6500 transitions. Word has length 96 [2018-11-23 07:24:12,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:12,268 INFO L480 AbstractCegarLoop]: Abstraction has 2498 states and 6500 transitions. [2018-11-23 07:24:12,268 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:12,268 INFO L276 IsEmpty]: Start isEmpty. Operand 2498 states and 6500 transitions. [2018-11-23 07:24:12,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:12,270 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:12,270 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:12,270 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:12,270 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:12,270 INFO L82 PathProgramCache]: Analyzing trace with hash 726758938, now seen corresponding path program 23 times [2018-11-23 07:24:12,270 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:12,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:12,274 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:24:12,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:12,274 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:12,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:13,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:13,073 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:13,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:13,073 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:13,073 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:13,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:13,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:13,073 INFO L87 Difference]: Start difference. First operand 2498 states and 6500 transitions. Second operand 21 states. [2018-11-23 07:24:13,784 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:13,962 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 39 [2018-11-23 07:24:14,135 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:24:14,332 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 48 [2018-11-23 07:24:14,511 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 07:24:14,732 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 53 [2018-11-23 07:24:15,165 WARN L180 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 51 [2018-11-23 07:24:15,353 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:24:15,575 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 62 [2018-11-23 07:24:16,012 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 55 [2018-11-23 07:24:16,184 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:24:16,380 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 53 [2018-11-23 07:24:16,553 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:24:16,721 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:24:16,871 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 47 [2018-11-23 07:24:17,087 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 51 [2018-11-23 07:24:17,256 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 47 [2018-11-23 07:24:17,398 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:24:17,646 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 54 [2018-11-23 07:24:17,769 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 50 [2018-11-23 07:24:17,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:17,779 INFO L93 Difference]: Finished difference Result 5297 states and 13147 transitions. [2018-11-23 07:24:17,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 07:24:17,779 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:17,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:17,783 INFO L225 Difference]: With dead ends: 5297 [2018-11-23 07:24:17,783 INFO L226 Difference]: Without dead ends: 5297 [2018-11-23 07:24:17,783 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 292 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=604, Invalid=1558, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 07:24:17,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5297 states. [2018-11-23 07:24:17,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5297 to 2465. [2018-11-23 07:24:17,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2465 states. [2018-11-23 07:24:17,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2465 states to 2465 states and 6401 transitions. [2018-11-23 07:24:17,809 INFO L78 Accepts]: Start accepts. Automaton has 2465 states and 6401 transitions. Word has length 96 [2018-11-23 07:24:17,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:17,810 INFO L480 AbstractCegarLoop]: Abstraction has 2465 states and 6401 transitions. [2018-11-23 07:24:17,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:17,810 INFO L276 IsEmpty]: Start isEmpty. Operand 2465 states and 6401 transitions. [2018-11-23 07:24:17,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:17,812 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:17,812 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:17,812 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:17,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:17,813 INFO L82 PathProgramCache]: Analyzing trace with hash -75703062, now seen corresponding path program 24 times [2018-11-23 07:24:17,813 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:17,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:17,816 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:17,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:17,816 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:17,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:18,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:18,648 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:18,649 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:18,649 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:18,649 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:18,649 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:18,649 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:18,649 INFO L87 Difference]: Start difference. First operand 2465 states and 6401 transitions. Second operand 21 states. [2018-11-23 07:24:19,322 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:19,490 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:24:19,783 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 07:24:19,952 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 47 [2018-11-23 07:24:20,142 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 51 [2018-11-23 07:24:20,333 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 07:24:20,550 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 62 [2018-11-23 07:24:20,949 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 43 [2018-11-23 07:24:21,126 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 45 [2018-11-23 07:24:21,287 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:24:21,514 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 07:24:21,804 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:24:22,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:22,088 INFO L93 Difference]: Finished difference Result 4435 states and 10826 transitions. [2018-11-23 07:24:22,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:22,088 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:22,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:22,090 INFO L225 Difference]: With dead ends: 4435 [2018-11-23 07:24:22,090 INFO L226 Difference]: Without dead ends: 4435 [2018-11-23 07:24:22,091 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=455, Invalid=1267, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:22,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4435 states. [2018-11-23 07:24:22,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4435 to 2467. [2018-11-23 07:24:22,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2467 states. [2018-11-23 07:24:22,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2467 states to 2467 states and 6406 transitions. [2018-11-23 07:24:22,113 INFO L78 Accepts]: Start accepts. Automaton has 2467 states and 6406 transitions. Word has length 96 [2018-11-23 07:24:22,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:22,113 INFO L480 AbstractCegarLoop]: Abstraction has 2467 states and 6406 transitions. [2018-11-23 07:24:22,113 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:22,113 INFO L276 IsEmpty]: Start isEmpty. Operand 2467 states and 6406 transitions. [2018-11-23 07:24:22,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:22,115 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:22,116 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:22,116 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:22,116 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:22,116 INFO L82 PathProgramCache]: Analyzing trace with hash -152659892, now seen corresponding path program 25 times [2018-11-23 07:24:22,116 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:22,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:22,119 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:22,119 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:22,119 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:22,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:22,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:22,950 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:22,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:22,950 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:22,951 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:22,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:22,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:22,951 INFO L87 Difference]: Start difference. First operand 2467 states and 6406 transitions. Second operand 21 states. [2018-11-23 07:24:23,621 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:23,783 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 38 [2018-11-23 07:24:24,072 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 41 [2018-11-23 07:24:24,261 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:24:24,455 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:24:24,641 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:24:24,853 WARN L180 SmtUtils]: Spent 178.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-23 07:24:25,254 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 42 [2018-11-23 07:24:25,424 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:24:25,582 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 07:24:25,714 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 41 [2018-11-23 07:24:26,076 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 41 [2018-11-23 07:24:26,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:26,326 INFO L93 Difference]: Finished difference Result 4332 states and 10629 transitions. [2018-11-23 07:24:26,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:26,327 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:26,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:26,329 INFO L225 Difference]: With dead ends: 4332 [2018-11-23 07:24:26,329 INFO L226 Difference]: Without dead ends: 4332 [2018-11-23 07:24:26,329 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=456, Invalid=1266, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:26,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4332 states. [2018-11-23 07:24:26,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4332 to 2465. [2018-11-23 07:24:26,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2465 states. [2018-11-23 07:24:26,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2465 states to 2465 states and 6401 transitions. [2018-11-23 07:24:26,350 INFO L78 Accepts]: Start accepts. Automaton has 2465 states and 6401 transitions. Word has length 96 [2018-11-23 07:24:26,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:26,350 INFO L480 AbstractCegarLoop]: Abstraction has 2465 states and 6401 transitions. [2018-11-23 07:24:26,350 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:26,350 INFO L276 IsEmpty]: Start isEmpty. Operand 2465 states and 6401 transitions. [2018-11-23 07:24:26,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:26,352 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:26,352 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:26,352 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:26,352 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:26,352 INFO L82 PathProgramCache]: Analyzing trace with hash 1933601036, now seen corresponding path program 26 times [2018-11-23 07:24:26,352 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:26,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:26,355 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:24:26,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:26,355 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:26,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:27,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:27,171 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:27,171 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:27,171 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:27,171 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:27,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:27,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:27,172 INFO L87 Difference]: Start difference. First operand 2465 states and 6401 transitions. Second operand 21 states. [2018-11-23 07:24:27,863 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:28,029 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 38 [2018-11-23 07:24:28,213 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 07:24:28,419 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:24:28,594 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:24:28,812 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 53 [2018-11-23 07:24:29,228 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 07:24:29,410 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 07:24:29,617 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 61 [2018-11-23 07:24:30,064 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:24:30,261 WARN L180 SmtUtils]: Spent 173.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 55 [2018-11-23 07:24:30,443 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 49 [2018-11-23 07:24:30,659 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 53 [2018-11-23 07:24:30,815 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:24:30,985 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 51 [2018-11-23 07:24:31,178 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 47 [2018-11-23 07:24:31,363 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 51 [2018-11-23 07:24:31,624 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 50 [2018-11-23 07:24:31,757 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:24:31,901 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 54 [2018-11-23 07:24:31,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:31,916 INFO L93 Difference]: Finished difference Result 6306 states and 15694 transitions. [2018-11-23 07:24:31,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-11-23 07:24:31,916 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:31,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:31,919 INFO L225 Difference]: With dead ends: 6306 [2018-11-23 07:24:31,919 INFO L226 Difference]: Without dead ends: 6306 [2018-11-23 07:24:31,919 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 287 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=605, Invalid=1557, Unknown=0, NotChecked=0, Total=2162 [2018-11-23 07:24:31,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6306 states. [2018-11-23 07:24:31,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6306 to 2476. [2018-11-23 07:24:31,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2476 states. [2018-11-23 07:24:31,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2476 states to 2476 states and 6434 transitions. [2018-11-23 07:24:31,945 INFO L78 Accepts]: Start accepts. Automaton has 2476 states and 6434 transitions. Word has length 96 [2018-11-23 07:24:31,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:31,945 INFO L480 AbstractCegarLoop]: Abstraction has 2476 states and 6434 transitions. [2018-11-23 07:24:31,945 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:31,945 INFO L276 IsEmpty]: Start isEmpty. Operand 2476 states and 6434 transitions. [2018-11-23 07:24:31,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:31,947 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:31,947 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:31,947 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:31,947 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:31,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1873385920, now seen corresponding path program 27 times [2018-11-23 07:24:31,948 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:31,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:31,952 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:31,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:31,952 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:31,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:32,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:32,844 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:32,844 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:32,844 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:32,844 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:32,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:32,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:32,844 INFO L87 Difference]: Start difference. First operand 2476 states and 6434 transitions. Second operand 21 states. [2018-11-23 07:24:33,523 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:33,687 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 38 [2018-11-23 07:24:33,871 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 07:24:34,074 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 49 [2018-11-23 07:24:34,438 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:24:34,643 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 07:24:34,829 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:24:35,046 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-23 07:24:35,469 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 51 [2018-11-23 07:24:35,654 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 49 [2018-11-23 07:24:35,815 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 47 [2018-11-23 07:24:36,220 WARN L180 SmtUtils]: Spent 149.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 47 [2018-11-23 07:24:36,483 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 50 [2018-11-23 07:24:36,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:36,496 INFO L93 Difference]: Finished difference Result 5188 states and 12863 transitions. [2018-11-23 07:24:36,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:36,496 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:36,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:36,499 INFO L225 Difference]: With dead ends: 5188 [2018-11-23 07:24:36,499 INFO L226 Difference]: Without dead ends: 5188 [2018-11-23 07:24:36,500 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=467, Invalid=1255, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:36,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5188 states. [2018-11-23 07:24:36,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5188 to 2454. [2018-11-23 07:24:36,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2454 states. [2018-11-23 07:24:36,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2454 states to 2454 states and 6368 transitions. [2018-11-23 07:24:36,524 INFO L78 Accepts]: Start accepts. Automaton has 2454 states and 6368 transitions. Word has length 96 [2018-11-23 07:24:36,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:36,525 INFO L480 AbstractCegarLoop]: Abstraction has 2454 states and 6368 transitions. [2018-11-23 07:24:36,525 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:36,525 INFO L276 IsEmpty]: Start isEmpty. Operand 2454 states and 6368 transitions. [2018-11-23 07:24:36,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:36,527 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:36,527 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:36,527 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:36,527 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:36,527 INFO L82 PathProgramCache]: Analyzing trace with hash 599463514, now seen corresponding path program 28 times [2018-11-23 07:24:36,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:36,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:36,531 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:36,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:36,531 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:36,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:37,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:37,350 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:37,350 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:37,350 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:37,350 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:37,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:37,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:37,351 INFO L87 Difference]: Start difference. First operand 2454 states and 6368 transitions. Second operand 21 states. [2018-11-23 07:24:38,045 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:38,273 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:24:38,442 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 42 [2018-11-23 07:24:38,613 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 47 [2018-11-23 07:24:38,805 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 51 [2018-11-23 07:24:38,993 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 52 [2018-11-23 07:24:39,207 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 62 [2018-11-23 07:24:39,560 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:24:39,715 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:24:39,855 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:24:40,301 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:24:40,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:40,550 INFO L93 Difference]: Finished difference Result 3450 states and 8352 transitions. [2018-11-23 07:24:40,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:40,551 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:40,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:40,553 INFO L225 Difference]: With dead ends: 3450 [2018-11-23 07:24:40,553 INFO L226 Difference]: Without dead ends: 3450 [2018-11-23 07:24:40,553 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 230 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=444, Invalid=1278, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:40,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3450 states. [2018-11-23 07:24:40,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3450 to 2448. [2018-11-23 07:24:40,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2448 states. [2018-11-23 07:24:40,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2448 states to 2448 states and 6353 transitions. [2018-11-23 07:24:40,575 INFO L78 Accepts]: Start accepts. Automaton has 2448 states and 6353 transitions. Word has length 96 [2018-11-23 07:24:40,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:40,575 INFO L480 AbstractCegarLoop]: Abstraction has 2448 states and 6353 transitions. [2018-11-23 07:24:40,576 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:40,576 INFO L276 IsEmpty]: Start isEmpty. Operand 2448 states and 6353 transitions. [2018-11-23 07:24:40,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:40,578 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:40,578 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:40,578 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:40,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:40,578 INFO L82 PathProgramCache]: Analyzing trace with hash 522506684, now seen corresponding path program 29 times [2018-11-23 07:24:40,578 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:40,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:40,582 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:24:40,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:40,582 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:40,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:41,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:41,432 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:41,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:41,432 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:41,432 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:41,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:41,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:41,432 INFO L87 Difference]: Start difference. First operand 2448 states and 6353 transitions. Second operand 21 states. [2018-11-23 07:24:42,129 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:42,382 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:24:42,555 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 41 [2018-11-23 07:24:42,751 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 48 [2018-11-23 07:24:42,959 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:24:43,145 WARN L180 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 52 [2018-11-23 07:24:43,361 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-23 07:24:43,783 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:24:43,950 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:24:44,092 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:24:44,552 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:24:44,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:44,812 INFO L93 Difference]: Finished difference Result 3668 states and 8805 transitions. [2018-11-23 07:24:44,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-11-23 07:24:44,812 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:44,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:44,814 INFO L225 Difference]: With dead ends: 3668 [2018-11-23 07:24:44,814 INFO L226 Difference]: Without dead ends: 3668 [2018-11-23 07:24:44,814 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 230 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=445, Invalid=1277, Unknown=0, NotChecked=0, Total=1722 [2018-11-23 07:24:44,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3668 states. [2018-11-23 07:24:44,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3668 to 2446. [2018-11-23 07:24:44,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2446 states. [2018-11-23 07:24:44,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2446 states to 2446 states and 6348 transitions. [2018-11-23 07:24:44,835 INFO L78 Accepts]: Start accepts. Automaton has 2446 states and 6348 transitions. Word has length 96 [2018-11-23 07:24:44,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:44,835 INFO L480 AbstractCegarLoop]: Abstraction has 2446 states and 6348 transitions. [2018-11-23 07:24:44,835 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:44,835 INFO L276 IsEmpty]: Start isEmpty. Operand 2446 states and 6348 transitions. [2018-11-23 07:24:44,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:44,836 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:44,836 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:44,837 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:44,837 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:44,837 INFO L82 PathProgramCache]: Analyzing trace with hash 1105380954, now seen corresponding path program 30 times [2018-11-23 07:24:44,837 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:44,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:44,839 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:44,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:44,840 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:44,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:45,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:45,674 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:45,674 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:45,674 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:45,674 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:45,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:45,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:45,675 INFO L87 Difference]: Start difference. First operand 2446 states and 6348 transitions. Second operand 21 states. [2018-11-23 07:24:46,358 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:46,604 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 46 DAG size of output: 37 [2018-11-23 07:24:46,764 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 42 [2018-11-23 07:24:46,932 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 46 [2018-11-23 07:24:47,143 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 49 [2018-11-23 07:24:47,357 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 53 [2018-11-23 07:24:47,548 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 53 [2018-11-23 07:24:47,778 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 62 [2018-11-23 07:24:48,136 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 38 [2018-11-23 07:24:48,294 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 40 [2018-11-23 07:24:48,438 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 39 [2018-11-23 07:24:48,883 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 37 [2018-11-23 07:24:49,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:49,115 INFO L93 Difference]: Finished difference Result 3402 states and 8279 transitions. [2018-11-23 07:24:49,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 07:24:49,115 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:49,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:49,118 INFO L225 Difference]: With dead ends: 3402 [2018-11-23 07:24:49,118 INFO L226 Difference]: Without dead ends: 3402 [2018-11-23 07:24:49,118 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 248 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=476, Invalid=1330, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:24:49,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3402 states. [2018-11-23 07:24:49,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3402 to 2440. [2018-11-23 07:24:49,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2440 states. [2018-11-23 07:24:49,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2440 states to 2440 states and 6333 transitions. [2018-11-23 07:24:49,138 INFO L78 Accepts]: Start accepts. Automaton has 2440 states and 6333 transitions. Word has length 96 [2018-11-23 07:24:49,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:49,138 INFO L480 AbstractCegarLoop]: Abstraction has 2440 states and 6333 transitions. [2018-11-23 07:24:49,138 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:49,138 INFO L276 IsEmpty]: Start isEmpty. Operand 2440 states and 6333 transitions. [2018-11-23 07:24:49,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:49,140 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:49,140 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:49,141 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:49,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:49,141 INFO L82 PathProgramCache]: Analyzing trace with hash -1420246442, now seen corresponding path program 31 times [2018-11-23 07:24:49,141 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:49,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:49,144 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:24:49,144 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:49,145 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:49,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:49,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:49,950 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:49,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:49,950 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:49,950 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:49,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:49,950 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:49,950 INFO L87 Difference]: Start difference. First operand 2440 states and 6333 transitions. Second operand 21 states. [2018-11-23 07:24:50,597 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:50,746 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 07:24:50,904 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:24:51,088 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 07:24:51,289 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 50 [2018-11-23 07:24:51,467 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:24:51,684 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 54 [2018-11-23 07:24:52,002 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 46 [2018-11-23 07:24:52,237 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 53 [2018-11-23 07:24:52,430 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 53 [2018-11-23 07:24:52,648 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 62 [2018-11-23 07:24:53,036 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 07:24:53,236 WARN L180 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 56 [2018-11-23 07:24:53,397 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 07:24:53,595 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 54 [2018-11-23 07:24:53,732 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 07:24:53,904 WARN L180 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 52 [2018-11-23 07:24:54,074 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 07:24:54,263 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 52 [2018-11-23 07:24:54,510 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 51 [2018-11-23 07:24:54,770 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 55 [2018-11-23 07:24:54,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:24:54,784 INFO L93 Difference]: Finished difference Result 4083 states and 10082 transitions. [2018-11-23 07:24:54,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-11-23 07:24:54,784 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:24:54,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:24:54,786 INFO L225 Difference]: With dead ends: 4083 [2018-11-23 07:24:54,787 INFO L226 Difference]: Without dead ends: 4083 [2018-11-23 07:24:54,787 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 339 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=653, Invalid=1699, Unknown=0, NotChecked=0, Total=2352 [2018-11-23 07:24:54,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4083 states. [2018-11-23 07:24:54,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4083 to 1967. [2018-11-23 07:24:54,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1967 states. [2018-11-23 07:24:54,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1967 states to 1967 states and 5046 transitions. [2018-11-23 07:24:54,806 INFO L78 Accepts]: Start accepts. Automaton has 1967 states and 5046 transitions. Word has length 96 [2018-11-23 07:24:54,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:24:54,806 INFO L480 AbstractCegarLoop]: Abstraction has 1967 states and 5046 transitions. [2018-11-23 07:24:54,806 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:24:54,806 INFO L276 IsEmpty]: Start isEmpty. Operand 1967 states and 5046 transitions. [2018-11-23 07:24:54,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:24:54,808 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:24:54,808 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:24:54,808 INFO L423 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:24:54,808 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:24:54,808 INFO L82 PathProgramCache]: Analyzing trace with hash -932266102, now seen corresponding path program 32 times [2018-11-23 07:24:54,809 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:24:54,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:54,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:24:54,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:24:54,812 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:24:54,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:24:55,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:24:55,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:24:55,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:24:55,666 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:24:55,666 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:24:55,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:24:55,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:24:55,667 INFO L87 Difference]: Start difference. First operand 1967 states and 5046 transitions. Second operand 21 states. [2018-11-23 07:24:56,400 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:24:56,550 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 07:24:56,729 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:24:56,967 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 44 [2018-11-23 07:24:57,220 WARN L180 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:24:57,682 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 07:24:57,954 WARN L180 SmtUtils]: Spent 212.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:24:58,199 WARN L180 SmtUtils]: Spent 202.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:24:58,390 WARN L180 SmtUtils]: Spent 166.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:24:58,620 WARN L180 SmtUtils]: Spent 185.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 62 [2018-11-23 07:24:59,059 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 07:24:59,248 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 52 [2018-11-23 07:24:59,412 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 07:24:59,644 WARN L180 SmtUtils]: Spent 206.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 50 [2018-11-23 07:24:59,825 WARN L180 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 07:25:00,028 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 48 [2018-11-23 07:25:00,164 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 49 DAG size of output: 42 [2018-11-23 07:25:00,343 WARN L180 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 46 [2018-11-23 07:25:00,558 WARN L180 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 07:25:00,779 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 48 [2018-11-23 07:25:00,956 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 42 [2018-11-23 07:25:01,104 WARN L180 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 47 [2018-11-23 07:25:01,261 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 07:25:01,436 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 51 [2018-11-23 07:25:01,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:01,459 INFO L93 Difference]: Finished difference Result 4336 states and 10537 transitions. [2018-11-23 07:25:01,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-11-23 07:25:01,460 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:25:01,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:01,462 INFO L225 Difference]: With dead ends: 4336 [2018-11-23 07:25:01,462 INFO L226 Difference]: Without dead ends: 4336 [2018-11-23 07:25:01,462 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=667, Invalid=1783, Unknown=0, NotChecked=0, Total=2450 [2018-11-23 07:25:01,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4336 states. [2018-11-23 07:25:01,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4336 to 1956. [2018-11-23 07:25:01,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1956 states. [2018-11-23 07:25:01,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1956 states to 1956 states and 5013 transitions. [2018-11-23 07:25:01,484 INFO L78 Accepts]: Start accepts. Automaton has 1956 states and 5013 transitions. Word has length 96 [2018-11-23 07:25:01,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:01,484 INFO L480 AbstractCegarLoop]: Abstraction has 1956 states and 5013 transitions. [2018-11-23 07:25:01,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:25:01,484 INFO L276 IsEmpty]: Start isEmpty. Operand 1956 states and 5013 transitions. [2018-11-23 07:25:01,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-11-23 07:25:01,486 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:01,486 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:01,486 INFO L423 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:01,486 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:01,486 INFO L82 PathProgramCache]: Analyzing trace with hash 197892122, now seen corresponding path program 33 times [2018-11-23 07:25:01,486 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:01,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:01,489 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:01,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:01,489 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:01,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:02,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:02,381 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:02,381 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-11-23 07:25:02,381 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:02,382 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 07:25:02,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 07:25:02,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=369, Unknown=0, NotChecked=0, Total=420 [2018-11-23 07:25:02,382 INFO L87 Difference]: Start difference. First operand 1956 states and 5013 transitions. Second operand 21 states. [2018-11-23 07:25:02,980 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 30 [2018-11-23 07:25:03,171 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 43 DAG size of output: 34 [2018-11-23 07:25:03,350 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 39 [2018-11-23 07:25:03,540 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 44 [2018-11-23 07:25:03,931 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 55 DAG size of output: 42 [2018-11-23 07:25:04,126 WARN L180 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 46 [2018-11-23 07:25:04,363 WARN L180 SmtUtils]: Spent 179.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 49 [2018-11-23 07:25:04,603 WARN L180 SmtUtils]: Spent 196.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:25:04,823 WARN L180 SmtUtils]: Spent 191.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 53 [2018-11-23 07:25:05,080 WARN L180 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 62 [2018-11-23 07:25:05,555 WARN L180 SmtUtils]: Spent 163.00 ms on a formula simplification. DAG size of input: 57 DAG size of output: 46 [2018-11-23 07:25:05,750 WARN L180 SmtUtils]: Spent 162.00 ms on a formula simplification. DAG size of input: 58 DAG size of output: 45 [2018-11-23 07:25:05,898 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 43 [2018-11-23 07:25:06,268 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 56 DAG size of output: 43 [2018-11-23 07:25:06,559 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 54 DAG size of output: 46 [2018-11-23 07:25:06,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:06,573 INFO L93 Difference]: Finished difference Result 2857 states and 6970 transitions. [2018-11-23 07:25:06,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-11-23 07:25:06,574 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 96 [2018-11-23 07:25:06,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:06,576 INFO L225 Difference]: With dead ends: 2857 [2018-11-23 07:25:06,576 INFO L226 Difference]: Without dead ends: 2857 [2018-11-23 07:25:06,577 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=488, Invalid=1318, Unknown=0, NotChecked=0, Total=1806 [2018-11-23 07:25:06,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2857 states. [2018-11-23 07:25:06,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2857 to 1778. [2018-11-23 07:25:06,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1778 states. [2018-11-23 07:25:06,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1778 states to 1778 states and 4648 transitions. [2018-11-23 07:25:06,596 INFO L78 Accepts]: Start accepts. Automaton has 1778 states and 4648 transitions. Word has length 96 [2018-11-23 07:25:06,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:06,596 INFO L480 AbstractCegarLoop]: Abstraction has 1778 states and 4648 transitions. [2018-11-23 07:25:06,596 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 07:25:06,597 INFO L276 IsEmpty]: Start isEmpty. Operand 1778 states and 4648 transitions. [2018-11-23 07:25:06,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:06,599 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:06,599 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:06,599 INFO L423 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:06,599 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:06,599 INFO L82 PathProgramCache]: Analyzing trace with hash 1217424457, now seen corresponding path program 1 times [2018-11-23 07:25:06,599 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:06,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:06,604 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:06,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:06,605 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:06,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:08,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:08,959 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:08,960 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [] total 32 [2018-11-23 07:25:08,960 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:08,960 INFO L459 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-11-23 07:25:08,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-11-23 07:25:08,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=911, Unknown=0, NotChecked=0, Total=992 [2018-11-23 07:25:08,960 INFO L87 Difference]: Start difference. First operand 1778 states and 4648 transitions. Second operand 32 states. [2018-11-23 07:25:09,948 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-23 07:25:10,130 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:25:10,374 WARN L180 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 07:25:10,610 WARN L180 SmtUtils]: Spent 153.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 07:25:10,833 WARN L180 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 54 [2018-11-23 07:25:11,078 WARN L180 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 57 [2018-11-23 07:25:11,310 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 59 [2018-11-23 07:25:12,887 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 65 [2018-11-23 07:25:13,199 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 69 [2018-11-23 07:25:13,346 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 63 [2018-11-23 07:25:13,603 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 71 [2018-11-23 07:25:13,758 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 65 [2018-11-23 07:25:13,914 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 62 [2018-11-23 07:25:15,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:15,090 INFO L93 Difference]: Finished difference Result 2141 states and 5467 transitions. [2018-11-23 07:25:15,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 07:25:15,090 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 102 [2018-11-23 07:25:15,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:15,091 INFO L225 Difference]: With dead ends: 2141 [2018-11-23 07:25:15,091 INFO L226 Difference]: Without dead ends: 1962 [2018-11-23 07:25:15,092 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 835 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=707, Invalid=3715, Unknown=0, NotChecked=0, Total=4422 [2018-11-23 07:25:15,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1962 states. [2018-11-23 07:25:15,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1962 to 1778. [2018-11-23 07:25:15,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1778 states. [2018-11-23 07:25:15,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1778 states to 1778 states and 4636 transitions. [2018-11-23 07:25:15,105 INFO L78 Accepts]: Start accepts. Automaton has 1778 states and 4636 transitions. Word has length 102 [2018-11-23 07:25:15,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:15,105 INFO L480 AbstractCegarLoop]: Abstraction has 1778 states and 4636 transitions. [2018-11-23 07:25:15,105 INFO L481 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-11-23 07:25:15,105 INFO L276 IsEmpty]: Start isEmpty. Operand 1778 states and 4636 transitions. [2018-11-23 07:25:15,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:15,106 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:15,106 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:15,106 INFO L423 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:15,106 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:15,107 INFO L82 PathProgramCache]: Analyzing trace with hash -269639387, now seen corresponding path program 2 times [2018-11-23 07:25:15,107 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:15,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:15,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:25:15,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:15,110 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:15,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:16,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:16,893 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:16,893 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2018-11-23 07:25:16,893 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:16,893 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-23 07:25:16,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-23 07:25:16,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=638, Unknown=0, NotChecked=0, Total=702 [2018-11-23 07:25:16,894 INFO L87 Difference]: Start difference. First operand 1778 states and 4636 transitions. Second operand 27 states. [2018-11-23 07:25:17,670 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-23 07:25:17,853 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:25:18,109 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 07:25:18,380 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 52 [2018-11-23 07:25:18,666 WARN L180 SmtUtils]: Spent 234.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 58 [2018-11-23 07:25:19,003 WARN L180 SmtUtils]: Spent 236.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 60 [2018-11-23 07:25:19,724 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 56 [2018-11-23 07:25:20,410 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 59 [2018-11-23 07:25:20,688 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 63 [2018-11-23 07:25:20,983 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 65 [2018-11-23 07:25:22,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:22,318 INFO L93 Difference]: Finished difference Result 2648 states and 6761 transitions. [2018-11-23 07:25:22,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-11-23 07:25:22,318 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 102 [2018-11-23 07:25:22,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:22,320 INFO L225 Difference]: With dead ends: 2648 [2018-11-23 07:25:22,320 INFO L226 Difference]: Without dead ends: 2508 [2018-11-23 07:25:22,320 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 684 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=611, Invalid=2929, Unknown=0, NotChecked=0, Total=3540 [2018-11-23 07:25:22,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2508 states. [2018-11-23 07:25:22,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2508 to 1822. [2018-11-23 07:25:22,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1822 states. [2018-11-23 07:25:22,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1822 states to 1822 states and 4753 transitions. [2018-11-23 07:25:22,335 INFO L78 Accepts]: Start accepts. Automaton has 1822 states and 4753 transitions. Word has length 102 [2018-11-23 07:25:22,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:22,336 INFO L480 AbstractCegarLoop]: Abstraction has 1822 states and 4753 transitions. [2018-11-23 07:25:22,336 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-23 07:25:22,336 INFO L276 IsEmpty]: Start isEmpty. Operand 1822 states and 4753 transitions. [2018-11-23 07:25:22,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:22,337 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:22,337 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:22,337 INFO L423 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:22,337 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:22,337 INFO L82 PathProgramCache]: Analyzing trace with hash -834712183, now seen corresponding path program 3 times [2018-11-23 07:25:22,337 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:22,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:22,341 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:22,341 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:22,341 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:22,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:24,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:24,580 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:24,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [34] imperfect sequences [] total 34 [2018-11-23 07:25:24,580 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:24,580 INFO L459 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-11-23 07:25:24,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-11-23 07:25:24,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=1034, Unknown=0, NotChecked=0, Total=1122 [2018-11-23 07:25:24,580 INFO L87 Difference]: Start difference. First operand 1822 states and 4753 transitions. Second operand 34 states. [2018-11-23 07:25:25,562 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-23 07:25:25,762 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:25:26,068 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 07:25:26,369 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 07:25:26,637 WARN L180 SmtUtils]: Spent 203.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 54 [2018-11-23 07:25:26,947 WARN L180 SmtUtils]: Spent 213.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 57 [2018-11-23 07:25:27,257 WARN L180 SmtUtils]: Spent 219.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 59 [2018-11-23 07:25:28,214 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 60 [2018-11-23 07:25:28,596 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 64 [2018-11-23 07:25:29,629 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 67 [2018-11-23 07:25:29,799 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 60 [2018-11-23 07:25:30,014 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 94 DAG size of output: 69 [2018-11-23 07:25:30,182 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 62 [2018-11-23 07:25:30,342 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 62 [2018-11-23 07:25:31,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:31,542 INFO L93 Difference]: Finished difference Result 2315 states and 5965 transitions. [2018-11-23 07:25:31,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 07:25:31,543 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 102 [2018-11-23 07:25:31,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:31,544 INFO L225 Difference]: With dead ends: 2315 [2018-11-23 07:25:31,545 INFO L226 Difference]: Without dead ends: 2188 [2018-11-23 07:25:31,545 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 878 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=728, Invalid=3964, Unknown=0, NotChecked=0, Total=4692 [2018-11-23 07:25:31,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2188 states. [2018-11-23 07:25:31,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2188 to 1910. [2018-11-23 07:25:31,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1910 states. [2018-11-23 07:25:31,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1910 states to 1910 states and 4987 transitions. [2018-11-23 07:25:31,561 INFO L78 Accepts]: Start accepts. Automaton has 1910 states and 4987 transitions. Word has length 102 [2018-11-23 07:25:31,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:31,561 INFO L480 AbstractCegarLoop]: Abstraction has 1910 states and 4987 transitions. [2018-11-23 07:25:31,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-11-23 07:25:31,562 INFO L276 IsEmpty]: Start isEmpty. Operand 1910 states and 4987 transitions. [2018-11-23 07:25:31,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:31,563 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:31,564 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:31,564 INFO L423 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:31,564 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:31,564 INFO L82 PathProgramCache]: Analyzing trace with hash -246222519, now seen corresponding path program 4 times [2018-11-23 07:25:31,564 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:31,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:31,570 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:31,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:31,570 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:31,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:33,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:33,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:33,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 07:25:33,499 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:33,500 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 07:25:33,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 07:25:33,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=973, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 07:25:33,500 INFO L87 Difference]: Start difference. First operand 1910 states and 4987 transitions. Second operand 33 states. [2018-11-23 07:25:34,482 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 07:25:34,726 WARN L180 SmtUtils]: Spent 142.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 07:25:34,977 WARN L180 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 07:25:35,201 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 56 [2018-11-23 07:25:35,449 WARN L180 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 59 [2018-11-23 07:25:35,696 WARN L180 SmtUtils]: Spent 183.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 61 [2018-11-23 07:25:36,699 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 66 [2018-11-23 07:25:37,243 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 68 [2018-11-23 07:25:37,565 WARN L180 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 61 [2018-11-23 07:25:38,348 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 64 [2018-11-23 07:25:39,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:39,898 INFO L93 Difference]: Finished difference Result 2447 states and 6262 transitions. [2018-11-23 07:25:39,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-11-23 07:25:39,898 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 07:25:39,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:39,899 INFO L225 Difference]: With dead ends: 2447 [2018-11-23 07:25:39,899 INFO L226 Difference]: Without dead ends: 2183 [2018-11-23 07:25:39,900 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1038 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=847, Invalid=4409, Unknown=0, NotChecked=0, Total=5256 [2018-11-23 07:25:39,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2183 states. [2018-11-23 07:25:39,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2183 to 1954. [2018-11-23 07:25:39,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1954 states. [2018-11-23 07:25:39,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1954 states to 1954 states and 5064 transitions. [2018-11-23 07:25:39,919 INFO L78 Accepts]: Start accepts. Automaton has 1954 states and 5064 transitions. Word has length 102 [2018-11-23 07:25:39,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:39,919 INFO L480 AbstractCegarLoop]: Abstraction has 1954 states and 5064 transitions. [2018-11-23 07:25:39,919 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 07:25:39,920 INFO L276 IsEmpty]: Start isEmpty. Operand 1954 states and 5064 transitions. [2018-11-23 07:25:39,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:39,921 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:39,921 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:39,921 INFO L423 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:39,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:39,922 INFO L82 PathProgramCache]: Analyzing trace with hash 725942285, now seen corresponding path program 5 times [2018-11-23 07:25:39,922 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:39,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:39,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:25:39,925 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:39,925 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:39,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:41,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:41,552 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:41,552 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [27] imperfect sequences [] total 27 [2018-11-23 07:25:41,552 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:41,552 INFO L459 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-11-23 07:25:41,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-11-23 07:25:41,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=640, Unknown=0, NotChecked=0, Total=702 [2018-11-23 07:25:41,553 INFO L87 Difference]: Start difference. First operand 1954 states and 5064 transitions. Second operand 27 states. [2018-11-23 07:25:42,394 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2018-11-23 07:25:42,617 WARN L180 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 50 [2018-11-23 07:25:42,887 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 55 [2018-11-23 07:25:43,129 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 82 DAG size of output: 61 [2018-11-23 07:25:43,411 WARN L180 SmtUtils]: Spent 188.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 63 [2018-11-23 07:25:44,066 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 58 [2018-11-23 07:25:44,379 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 62 [2018-11-23 07:25:44,702 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 69 DAG size of output: 54 [2018-11-23 07:25:44,959 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 64 [2018-11-23 07:25:45,131 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 56 [2018-11-23 07:25:45,579 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 67 [2018-11-23 07:25:45,751 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 59 [2018-11-23 07:25:45,936 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 62 [2018-11-23 07:25:46,099 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 65 DAG size of output: 59 [2018-11-23 07:25:46,352 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 56 [2018-11-23 07:25:47,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:47,814 INFO L93 Difference]: Finished difference Result 2635 states and 6663 transitions. [2018-11-23 07:25:47,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-23 07:25:47,814 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 102 [2018-11-23 07:25:47,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:47,816 INFO L225 Difference]: With dead ends: 2635 [2018-11-23 07:25:47,816 INFO L226 Difference]: Without dead ends: 2214 [2018-11-23 07:25:47,816 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 832 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=712, Invalid=3448, Unknown=0, NotChecked=0, Total=4160 [2018-11-23 07:25:47,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2214 states. [2018-11-23 07:25:47,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2214 to 1634. [2018-11-23 07:25:47,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1634 states. [2018-11-23 07:25:47,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1634 states to 1634 states and 4228 transitions. [2018-11-23 07:25:47,832 INFO L78 Accepts]: Start accepts. Automaton has 1634 states and 4228 transitions. Word has length 102 [2018-11-23 07:25:47,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:47,832 INFO L480 AbstractCegarLoop]: Abstraction has 1634 states and 4228 transitions. [2018-11-23 07:25:47,832 INFO L481 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-11-23 07:25:47,833 INFO L276 IsEmpty]: Start isEmpty. Operand 1634 states and 4228 transitions. [2018-11-23 07:25:47,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:47,834 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:47,834 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:47,834 INFO L423 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:47,834 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:47,834 INFO L82 PathProgramCache]: Analyzing trace with hash 1534034829, now seen corresponding path program 6 times [2018-11-23 07:25:47,834 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:47,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:47,838 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:47,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:47,838 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:47,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:49,579 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 24 [2018-11-23 07:25:50,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:50,187 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:50,188 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 07:25:50,188 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:50,188 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 07:25:50,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 07:25:50,188 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=974, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 07:25:50,188 INFO L87 Difference]: Start difference. First operand 1634 states and 4228 transitions. Second operand 33 states. [2018-11-23 07:25:51,225 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 07:25:51,473 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 07:25:51,730 WARN L180 SmtUtils]: Spent 158.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 07:25:51,947 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 56 [2018-11-23 07:25:52,213 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 63 [2018-11-23 07:25:52,476 WARN L180 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 65 [2018-11-23 07:25:53,556 WARN L180 SmtUtils]: Spent 193.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 64 [2018-11-23 07:25:54,039 WARN L180 SmtUtils]: Spent 105.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 65 [2018-11-23 07:25:54,466 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2018-11-23 07:25:54,865 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 111 DAG size of output: 74 [2018-11-23 07:25:55,062 WARN L180 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 67 [2018-11-23 07:25:55,221 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 64 [2018-11-23 07:25:56,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:25:56,366 INFO L93 Difference]: Finished difference Result 1939 states and 4894 transitions. [2018-11-23 07:25:56,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 07:25:56,366 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 07:25:56,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:25:56,367 INFO L225 Difference]: With dead ends: 1939 [2018-11-23 07:25:56,367 INFO L226 Difference]: Without dead ends: 1760 [2018-11-23 07:25:56,368 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 798 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=730, Invalid=3826, Unknown=0, NotChecked=0, Total=4556 [2018-11-23 07:25:56,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1760 states. [2018-11-23 07:25:56,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1760 to 1640. [2018-11-23 07:25:56,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1640 states. [2018-11-23 07:25:56,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1640 states to 1640 states and 4237 transitions. [2018-11-23 07:25:56,381 INFO L78 Accepts]: Start accepts. Automaton has 1640 states and 4237 transitions. Word has length 102 [2018-11-23 07:25:56,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:25:56,381 INFO L480 AbstractCegarLoop]: Abstraction has 1640 states and 4237 transitions. [2018-11-23 07:25:56,382 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 07:25:56,382 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 4237 transitions. [2018-11-23 07:25:56,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:25:56,383 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:25:56,383 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:25:56,383 INFO L423 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:25:56,383 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:25:56,383 INFO L82 PathProgramCache]: Analyzing trace with hash -1102092123, now seen corresponding path program 7 times [2018-11-23 07:25:56,383 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:25:56,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:56,386 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:25:56,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:25:56,386 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:25:56,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:25:58,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:25:58,384 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:25:58,384 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 07:25:58,384 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:25:58,384 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 07:25:58,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 07:25:58,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=974, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 07:25:58,384 INFO L87 Difference]: Start difference. First operand 1640 states and 4237 transitions. Second operand 33 states. [2018-11-23 07:25:59,349 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 41 [2018-11-23 07:25:59,612 WARN L180 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 49 [2018-11-23 07:25:59,863 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 51 [2018-11-23 07:26:00,082 WARN L180 SmtUtils]: Spent 167.00 ms on a formula simplification. DAG size of input: 80 DAG size of output: 56 [2018-11-23 07:26:00,339 WARN L180 SmtUtils]: Spent 181.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 63 [2018-11-23 07:26:00,602 WARN L180 SmtUtils]: Spent 191.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 65 [2018-11-23 07:26:01,703 WARN L180 SmtUtils]: Spent 195.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 64 [2018-11-23 07:26:02,014 WARN L180 SmtUtils]: Spent 216.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 68 [2018-11-23 07:26:02,167 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 63 [2018-11-23 07:26:02,594 WARN L180 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 69 [2018-11-23 07:26:03,106 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 71 [2018-11-23 07:26:03,311 WARN L180 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 63 [2018-11-23 07:26:03,508 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 68 [2018-11-23 07:26:03,839 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 83 DAG size of output: 62 [2018-11-23 07:26:04,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:26:04,875 INFO L93 Difference]: Finished difference Result 1895 states and 4796 transitions. [2018-11-23 07:26:04,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-11-23 07:26:04,875 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 07:26:04,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:26:04,876 INFO L225 Difference]: With dead ends: 1895 [2018-11-23 07:26:04,876 INFO L226 Difference]: Without dead ends: 1755 [2018-11-23 07:26:04,877 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 789 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=749, Invalid=3807, Unknown=0, NotChecked=0, Total=4556 [2018-11-23 07:26:04,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1755 states. [2018-11-23 07:26:04,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1755 to 1642. [2018-11-23 07:26:04,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1642 states. [2018-11-23 07:26:04,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1642 states to 1642 states and 4240 transitions. [2018-11-23 07:26:04,891 INFO L78 Accepts]: Start accepts. Automaton has 1642 states and 4240 transitions. Word has length 102 [2018-11-23 07:26:04,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:26:04,891 INFO L480 AbstractCegarLoop]: Abstraction has 1642 states and 4240 transitions. [2018-11-23 07:26:04,891 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 07:26:04,891 INFO L276 IsEmpty]: Start isEmpty. Operand 1642 states and 4240 transitions. [2018-11-23 07:26:04,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:26:04,892 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:26:04,892 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:26:04,893 INFO L423 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:26:04,893 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:26:04,893 INFO L82 PathProgramCache]: Analyzing trace with hash -605787191, now seen corresponding path program 8 times [2018-11-23 07:26:04,893 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:26:04,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:04,896 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:26:04,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:04,896 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:26:04,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:26:07,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:26:07,229 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:26:07,229 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [33] imperfect sequences [] total 33 [2018-11-23 07:26:07,229 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:26:07,229 INFO L459 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-11-23 07:26:07,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-11-23 07:26:07,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=971, Unknown=0, NotChecked=0, Total=1056 [2018-11-23 07:26:07,230 INFO L87 Difference]: Start difference. First operand 1642 states and 4240 transitions. Second operand 33 states. [2018-11-23 07:26:08,088 WARN L180 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 41 [2018-11-23 07:26:08,268 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 39 [2018-11-23 07:26:08,529 WARN L180 SmtUtils]: Spent 151.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 47 [2018-11-23 07:26:08,810 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 49 [2018-11-23 07:26:09,051 WARN L180 SmtUtils]: Spent 184.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 54 [2018-11-23 07:26:09,340 WARN L180 SmtUtils]: Spent 203.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 61 [2018-11-23 07:26:09,640 WARN L180 SmtUtils]: Spent 216.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 63 [2018-11-23 07:26:10,869 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 62 [2018-11-23 07:26:11,209 WARN L180 SmtUtils]: Spent 235.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 66 [2018-11-23 07:26:11,539 WARN L180 SmtUtils]: Spent 263.00 ms on a formula simplification. DAG size of input: 112 DAG size of output: 70 [2018-11-23 07:26:11,893 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 63 [2018-11-23 07:26:12,312 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 65 [2018-11-23 07:26:12,500 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 58 [2018-11-23 07:26:12,825 WARN L180 SmtUtils]: Spent 128.00 ms on a formula simplification. DAG size of input: 106 DAG size of output: 66 [2018-11-23 07:26:13,163 WARN L180 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 64 [2018-11-23 07:26:14,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:26:14,487 INFO L93 Difference]: Finished difference Result 1972 states and 4919 transitions. [2018-11-23 07:26:14,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-11-23 07:26:14,487 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 102 [2018-11-23 07:26:14,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:26:14,488 INFO L225 Difference]: With dead ends: 1972 [2018-11-23 07:26:14,489 INFO L226 Difference]: Without dead ends: 1845 [2018-11-23 07:26:14,489 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 973 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=837, Invalid=4133, Unknown=0, NotChecked=0, Total=4970 [2018-11-23 07:26:14,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1845 states. [2018-11-23 07:26:14,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1845 to 1646. [2018-11-23 07:26:14,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1646 states. [2018-11-23 07:26:14,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1646 states to 1646 states and 4246 transitions. [2018-11-23 07:26:14,504 INFO L78 Accepts]: Start accepts. Automaton has 1646 states and 4246 transitions. Word has length 102 [2018-11-23 07:26:14,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:26:14,504 INFO L480 AbstractCegarLoop]: Abstraction has 1646 states and 4246 transitions. [2018-11-23 07:26:14,504 INFO L481 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-11-23 07:26:14,504 INFO L276 IsEmpty]: Start isEmpty. Operand 1646 states and 4246 transitions. [2018-11-23 07:26:14,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:26:14,506 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:26:14,506 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:26:14,507 INFO L423 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:26:14,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:26:14,507 INFO L82 PathProgramCache]: Analyzing trace with hash 407867661, now seen corresponding path program 1 times [2018-11-23 07:26:14,507 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:26:14,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:14,512 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 07:26:14,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:14,512 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:26:14,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 07:26:15,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 07:26:15,196 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 07:26:15,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-11-23 07:26:15,196 INFO L256 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-11-23 07:26:15,196 INFO L459 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-11-23 07:26:15,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-11-23 07:26:15,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2018-11-23 07:26:15,197 INFO L87 Difference]: Start difference. First operand 1646 states and 4246 transitions. Second operand 20 states. [2018-11-23 07:26:16,113 WARN L180 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 37 [2018-11-23 07:26:17,370 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 33 [2018-11-23 07:26:17,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 07:26:17,436 INFO L93 Difference]: Finished difference Result 2412 states and 6128 transitions. [2018-11-23 07:26:17,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 07:26:17,437 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 102 [2018-11-23 07:26:17,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 07:26:17,440 INFO L225 Difference]: With dead ends: 2412 [2018-11-23 07:26:17,440 INFO L226 Difference]: Without dead ends: 2377 [2018-11-23 07:26:17,440 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 121 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=382, Invalid=878, Unknown=0, NotChecked=0, Total=1260 [2018-11-23 07:26:17,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2018-11-23 07:26:17,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 1914. [2018-11-23 07:26:17,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1914 states. [2018-11-23 07:26:17,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 4893 transitions. [2018-11-23 07:26:17,468 INFO L78 Accepts]: Start accepts. Automaton has 1914 states and 4893 transitions. Word has length 102 [2018-11-23 07:26:17,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 07:26:17,469 INFO L480 AbstractCegarLoop]: Abstraction has 1914 states and 4893 transitions. [2018-11-23 07:26:17,469 INFO L481 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-11-23 07:26:17,469 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 4893 transitions. [2018-11-23 07:26:17,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-11-23 07:26:17,471 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 07:26:17,471 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 07:26:17,472 INFO L423 AbstractCegarLoop]: === Iteration 48 === [ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 07:26:17,472 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 07:26:17,472 INFO L82 PathProgramCache]: Analyzing trace with hash -1623962551, now seen corresponding path program 9 times [2018-11-23 07:26:17,472 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-11-23 07:26:17,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:17,478 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 07:26:17,478 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 07:26:17,478 INFO L286 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-11-23 07:26:17,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 07:26:17,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 07:26:17,568 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [287] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [202] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [276] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [272] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [278] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 [280] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 [277] L3774-4-->L-1-1: Formula: (and (= v_~my_dev~0.base_1 0) (= v_~my_dev~0.offset_1 0)) InVars {} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_1, ~my_dev~0.base=v_~my_dev~0.base_1} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [308] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [307] L-1-2-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_1|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret40, ULTIMATE.start_main_#t~mem42, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [204] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [195] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [318] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret40_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [214] L3847-1-->L3847-2: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret40_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret40_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [209] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret40_4|) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [191] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [285] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [253] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [196] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [314] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [284] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [283] L3851-1-->L3805: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_1|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31, ULTIMATE.start_my_drv_probe_#t~mem32, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet35, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [252] L3805-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3) v_ULTIMATE.start_my_drv_probe_~data.offset_3 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [309] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0)))) (= (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0))) |v_#memory_$Pointer$.base_1|) (= |v_#memory_int_3| (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 0))))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [306] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 44))) (and (= |v_#memory_$Pointer$.base_3| (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_int_5| (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0))) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [267] L3810-->L3811: Formula: (= (select (select |v_#memory_int_7| v_ULTIMATE.start_my_drv_probe_~data.base_6) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 40)) |v_ULTIMATE.start_my_drv_probe_#t~mem31_2|) InVars {#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} OutVars{#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [224] L3811-->L3811-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem31_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [219] L3811-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [259] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [262] L3772-1-->L3772-4: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_4)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [239] L3772-4-->L3812: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [296] L3812-->L3812-1: Formula: (= (select (select |v_#memory_int_8| v_ULTIMATE.start_my_drv_probe_~data.base_7) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_7 44)) |v_ULTIMATE.start_my_drv_probe_#t~mem32_2|) InVars {#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} OutVars{#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [299] L3812-1-->L3812-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_3| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem32_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [294] L3812-2-->L3772-5: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_5} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [241] L3772-5-->L3772-6: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_6 |v_ULTIMATE.start_ldv_assert_#in~expression_4|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_6} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [249] L3772-6-->L3772-9: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_8)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [233] L3772-9-->L3814: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [211] L3814-->L3814-1: Formula: (and (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483648)) (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483647)) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [210] L3814-1-->L3814-2: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [189] L3814-2-->L3815: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [289] L3815-->L3819: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [250] L3819-->L3822: Formula: (and (= v_~my_dev~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_8) (= v_~my_dev~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_8 40))) InVars {ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_2, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8, ~my_dev~0.base=v_~my_dev~0.base_2} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [222] L3822-->L3822-1: Formula: (and (= (store |v_#memory_int_10| |v_~#t1~0.base_3| (store (select |v_#memory_int_10| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0)) |v_#memory_int_9|) (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_10|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_9|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 [340] L3822-1-->my_callbackENTRY: Formula: (and (= 0 |v_Thread0_my_callback_#in~arg.offset_3|) (= 0 |v_Thread0_my_callback_#in~arg.base_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {} OutVars{Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [320] my_callbackENTRY-->L3794: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [321] L3794-->L3795: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [226] L3822-2-->L3823: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [322] L3795-->L3795-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread0_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1, ~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [323] L3795-1-->L3799: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [324] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread0_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread0_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [325] L3799-1-->L3800: Formula: (= |v_Thread0_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread0_my_callback_~data~0.base_4) (+ v_Thread0_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} OutVars{#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [302] L3823-->L3823-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_~#t2~0.base_3| (store (select |v_#memory_int_12| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_12|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_11|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 [341] L3823-1-->my_callbackENTRY: Formula: (and (= |v_Thread1_my_callback_#in~arg.base_3| 0) (= 0 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {} OutVars{Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [292] L3823-2-->L3824: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [264] L3824-->L3828: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [330] my_callbackENTRY-->L3794: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [331] L3794-->L3795: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [315] L3828-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [275] L3851-2-->L3851-3: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [273] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [274] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [304] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [310] L3853-1-->L3831: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem36, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [305] L3831-->L3832: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [266] L3832-->L3832-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [268] L3832-1-->L3833: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2| (select (select |v_#memory_int_13| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [332] L3795-->L3795-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread1_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [333] L3795-1-->L3799: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [334] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread1_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread1_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [335] L3799-1-->L3800: Formula: (= |v_Thread1_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread1_my_callback_~data~0.base_4) (+ v_Thread1_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} OutVars{#memory_int=|v_#memory_int_29|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_1|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [336] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5) .cse0 (+ |v_Thread1_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [337] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [338] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread1_my_callback_#res.offset_1| 0) (= |v_Thread1_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_1|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_#res.offset, Thread1_my_callback_#res.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [339] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [326] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5) .cse0 (+ |v_Thread0_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [327] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [328] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [329] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 [342] my_callbackEXIT-->L3833-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5| v_Thread0_my_callback_thidvar0_4) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|) (= |v_Thread0_my_callback_#res.base_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [217] L3833-1-->L3833-2: Formula: (and (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|)) |v_#memory_$Pointer$.base_9|) (= (store |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_14| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_14|)) InVars {ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_15|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [220] L3833-2-->L3833-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [229] L3833-3-->L3834: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [303] L3834-->L3834-1: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2| (select (select |v_#memory_int_16| |v_~#t2~0.base_4|) |v_~#t2~0.offset_4|)) InVars {#memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2|, #memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 [345] my_callbackEXIT-->L3834-2: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7| |v_Thread1_my_callback_#res.offset_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7| |v_Thread1_my_callback_#res.base_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7| v_Thread1_my_callback_thidvar0_6)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7|, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [293] L3834-2-->L3834-3: Formula: (and (= (store |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|)) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|))) (= (store |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| (select (select |v_#memory_int_17| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|))) |v_#memory_int_17|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_18|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_17|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [295] L3834-3-->L3834-4: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [300] L3834-4-->L3832-2: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [271] L3832-2-->L3832-3: Formula: (= (store |v_#valid_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5| 0) |v_#valid_11|) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [270] L3832-3-->L3831-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_6|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_6|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [311] L3831-1-->L3854: Formula: (= (select (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#data~1.base_5|) (+ |v_ULTIMATE.start_main_~#data~1.offset_5| 40)) |v_ULTIMATE.start_main_#t~mem42_2|) InVars {#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} OutVars{#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_2|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [269] L3854-->L3854-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_5| (ite (= |v_ULTIMATE.start_main_#t~mem42_3| 1) 1 0)) InVars {ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [265] L3854-1-->L3772-10: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_9} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [232] L3772-10-->L3772-11: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_10 |v_ULTIMATE.start_ldv_assert_#in~expression_6|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_10} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [238] L3772-11-->L3772-14: Formula: (not (= v_ULTIMATE.start_ldv_assert_~expression_12 0)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [223] L3772-14-->L3855: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [236] L3855-->L3855-1: Formula: (= |v_ULTIMATE.start_main_#t~mem43_2| (select (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#data~1.base_6|) (+ |v_ULTIMATE.start_main_~#data~1.offset_6| 44))) InVars {#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_2|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem43] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [225] L3855-1-->L3855-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_7| (ite (= |v_ULTIMATE.start_main_#t~mem43_3| 2) 1 0)) InVars {ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_7|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [215] L3855-2-->L3772-15: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_13} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [218] L3772-15-->L3772-16: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_14 |v_ULTIMATE.start_ldv_assert_#in~expression_8|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_14} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [227] L3772-16-->L3772-17: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_15 0) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [230] L3772-17-->ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={60:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={63:40}, t1={69:0}, t2={60:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3824] -1 return 0; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 1 struct my_data *data; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3832] -1 void *status; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] -1 \read(t1) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] ----- [2018-11-23 07:26:19,741 INFO L305 ceAbstractionStarter]: Did not count any witness invariants because Icfg is not BoogieIcfg [2018-11-23 07:26:19,742 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 07:26:19 BasicIcfg [2018-11-23 07:26:19,742 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 07:26:19,742 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 07:26:19,742 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 07:26:19,742 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 07:26:19,743 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 07:22:33" (3/4) ... [2018-11-23 07:26:19,745 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.modelcheckerutils.cfg.transformations.BlockEncodingBacktranslator [?] -1 [287] ULTIMATE.startENTRY-->L-1: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [202] L-1-->L3774: Formula: (= |v_#valid_1| (store |v_#valid_2| 0 0)) InVars {#valid=|v_#valid_2|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid] VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 [276] L3774-->L3774-1: Formula: (and (= (select |v_#valid_4| |v_~#t1~0.base_1|) 0) (not (= |v_~#t1~0.base_1| 0)) (= 0 |v_~#t1~0.offset_1|) (= |v_#length_1| (store |v_#length_2| |v_~#t1~0.base_1| 4)) (= (store |v_#valid_4| |v_~#t1~0.base_1| 1) |v_#valid_3|)) InVars {#length=|v_#length_2|, #valid=|v_#valid_4|} OutVars{~#t1~0.offset=|v_~#t1~0.offset_1|, #length=|v_#length_1|, ~#t1~0.base=|v_~#t1~0.base_1|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[~#t1~0.base, #valid, ~#t1~0.offset, #length] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [272] L3774-1-->L3774-2: Formula: (= 0 (select (select |v_#memory_int_1| |v_~#t1~0.base_2|) |v_~#t1~0.offset_2|)) InVars {#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} OutVars{#memory_int=|v_#memory_int_1|, ~#t1~0.offset=|v_~#t1~0.offset_2|, ~#t1~0.base=|v_~#t1~0.base_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 [278] L3774-2-->L3774-3: Formula: (and (= 0 (select |v_#valid_6| |v_~#t2~0.base_1|)) (= (store |v_#length_4| |v_~#t2~0.base_1| 4) |v_#length_3|) (not (= 0 |v_~#t2~0.base_1|)) (= 0 |v_~#t2~0.offset_1|) (= |v_#valid_5| (store |v_#valid_6| |v_~#t2~0.base_1| 1))) InVars {#length=|v_#length_4|, #valid=|v_#valid_6|} OutVars{#length=|v_#length_3|, ~#t2~0.base=|v_~#t2~0.base_1|, ~#t2~0.offset=|v_~#t2~0.offset_1|, #valid=|v_#valid_5|} AuxVars[] AssignedVars[~#t2~0.offset, #valid, #length, ~#t2~0.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 [280] L3774-3-->L3774-4: Formula: (= (select (select |v_#memory_int_2| |v_~#t2~0.base_2|) |v_~#t2~0.offset_2|) 0) InVars {#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} OutVars{#memory_int=|v_#memory_int_2|, ~#t2~0.base=|v_~#t2~0.base_2|, ~#t2~0.offset=|v_~#t2~0.offset_2|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 [277] L3774-4-->L-1-1: Formula: (and (= v_~my_dev~0.base_1 0) (= v_~my_dev~0.offset_1 0)) InVars {} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_1, ~my_dev~0.base=v_~my_dev~0.base_1} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [308] L-1-1-->L-1-2: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [307] L-1-2-->L3847: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem45=|v_ULTIMATE.start_main_#t~mem45_1|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_1|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_1, ULTIMATE.start_main_#t~mem44=|v_ULTIMATE.start_main_#t~mem44_1|, ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_1|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_1|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_1|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_1, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem45, ULTIMATE.start_main_#t~mem43, ULTIMATE.start_main_~ret~0, ULTIMATE.start_main_#t~mem44, ULTIMATE.start_main_#t~ret40, ULTIMATE.start_main_#t~mem42, ULTIMATE.start_main_#t~ret41, ULTIMATE.start_main_~#data~1.offset, ULTIMATE.start_main_~probe_ret~0, ULTIMATE.start_main_~#data~1.base] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [204] L3847-->L3839: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [195] L3839-->L3839-1: Formula: (= |v_ULTIMATE.start_my_drv_init_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_init_#res] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [318] L3839-1-->L3847-1: Formula: (= |v_ULTIMATE.start_main_#t~ret40_2| |v_ULTIMATE.start_my_drv_init_#res_3|) InVars {ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_2|, ULTIMATE.start_my_drv_init_#res=|v_ULTIMATE.start_my_drv_init_#res_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [214] L3847-1-->L3847-2: Formula: (and (<= 0 (+ |v_ULTIMATE.start_main_#t~ret40_3| 2147483648)) (<= |v_ULTIMATE.start_main_#t~ret40_3| 2147483647)) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_3|} AuxVars[] AssignedVars[] VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [209] L3847-2-->L3847-3: Formula: (= v_ULTIMATE.start_main_~ret~0_2 |v_ULTIMATE.start_main_#t~ret40_4|) InVars {ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_4|, ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [191] L3847-3-->L3848: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret40=|v_ULTIMATE.start_main_#t~ret40_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret40] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [285] L3848-->L3849: Formula: (= v_ULTIMATE.start_main_~ret~0_3 0) InVars {ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} OutVars{ULTIMATE.start_main_~ret~0=v_ULTIMATE.start_main_~ret~0_3} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [253] L3849-->L3850: Formula: true InVars {} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_2} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [196] L3850-->L3850-1: Formula: (and (= 0 |v_ULTIMATE.start_main_~#data~1.offset_2|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2|) 0) (not (= |v_ULTIMATE.start_main_~#data~1.base_2| 0)) (= (store |v_#length_6| |v_ULTIMATE.start_main_~#data~1.base_2| 48) |v_#length_5|) (= (store |v_#valid_8| |v_ULTIMATE.start_main_~#data~1.base_2| 1) |v_#valid_7|)) InVars {#length=|v_#length_6|, #valid=|v_#valid_8|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_2|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[#valid, ULTIMATE.start_main_~#data~1.offset, #length, ULTIMATE.start_main_~#data~1.base] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [314] L3850-1-->L3851: Formula: (and (= |v_ULTIMATE.start_my_drv_probe_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_3|) (= |v_ULTIMATE.start_my_drv_probe_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_3|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_1|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_3|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_3|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#in~data.base, ULTIMATE.start_my_drv_probe_#in~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [284] L3851-->L3851-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [283] L3851-1-->L3805: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_1|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_1, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_1, ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_1|, ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_1|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_1, ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31, ULTIMATE.start_my_drv_probe_#t~mem32, ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset, ULTIMATE.start_my_drv_probe_#t~nondet33, ULTIMATE.start_my_drv_probe_#t~nondet35, ULTIMATE.start_my_drv_probe_~res~0, ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [252] L3805-->L3808: Formula: (and (= v_ULTIMATE.start_my_drv_probe_~data.offset_2 |v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|) (= v_ULTIMATE.start_my_drv_probe_~data.base_2 |v_ULTIMATE.start_my_drv_probe_#in~data.base_2|)) InVars {ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_probe_#in~data.base=|v_ULTIMATE.start_my_drv_probe_#in~data.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_2, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_2, ULTIMATE.start_my_drv_probe_#in~data.offset=|v_ULTIMATE.start_my_drv_probe_#in~data.offset_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~data.base, ULTIMATE.start_my_drv_probe_~data.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [242] L3808-->L3809: Formula: (= |v_#pthreadsMutex_1| (store |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3 (store (select |v_#pthreadsMutex_2| v_ULTIMATE.start_my_drv_probe_~data.base_3) v_ULTIMATE.start_my_drv_probe_~data.offset_3 0))) InVars {#pthreadsMutex=|v_#pthreadsMutex_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} OutVars{#pthreadsMutex=|v_#pthreadsMutex_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_3, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_3} AuxVars[] AssignedVars[#pthreadsMutex] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [309] L3809-->L3809-1: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_4 40))) (and (= |v_#memory_$Pointer$.offset_1| (store |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.offset_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.offset_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0)))) (= (store |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_$Pointer$.base_2| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 (select (select |v_#memory_$Pointer$.base_1| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0))) |v_#memory_$Pointer$.base_1|) (= |v_#memory_int_3| (store |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4 (store (select |v_#memory_int_4| v_ULTIMATE.start_my_drv_probe_~data.base_4) .cse0 0))))) InVars {#memory_int=|v_#memory_int_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_2|} OutVars{#memory_int=|v_#memory_int_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_1|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_4, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_4, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_1|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [306] L3809-1-->L3810: Formula: (let ((.cse0 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_5 44))) (and (= |v_#memory_$Pointer$.base_3| (store |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.base_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))) (= |v_#memory_int_5| (store |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_int_6| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 0))) (= |v_#memory_$Pointer$.offset_3| (store |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5 (store (select |v_#memory_$Pointer$.offset_4| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_3| v_ULTIMATE.start_my_drv_probe_~data.base_5) .cse0)))))) InVars {#memory_int=|v_#memory_int_6|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_4|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_4|} OutVars{#memory_int=|v_#memory_int_5|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_3|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_5, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [267] L3810-->L3811: Formula: (= (select (select |v_#memory_int_7| v_ULTIMATE.start_my_drv_probe_~data.base_6) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_6 40)) |v_ULTIMATE.start_my_drv_probe_#t~mem31_2|) InVars {#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} OutVars{#memory_int=|v_#memory_int_7|, ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_6, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_6} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [224] L3811-->L3811-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_1| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem31_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_1|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [219] L3811-1-->L3772: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_1} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [259] L3772-->L3772-1: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_2 |v_ULTIMATE.start_ldv_assert_#in~expression_2|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_2|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_2} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [262] L3772-1-->L3772-4: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_4)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [239] L3772-4-->L3812: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem31=|v_ULTIMATE.start_my_drv_probe_#t~mem31_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem31] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [296] L3812-->L3812-1: Formula: (= (select (select |v_#memory_int_8| v_ULTIMATE.start_my_drv_probe_~data.base_7) (+ v_ULTIMATE.start_my_drv_probe_~data.offset_7 44)) |v_ULTIMATE.start_my_drv_probe_#t~mem32_2|) InVars {#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} OutVars{#memory_int=|v_#memory_int_8|, ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_2|, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_7, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_7} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [299] L3812-1-->L3812-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_3| (ite (= 0 |v_ULTIMATE.start_my_drv_probe_#t~mem32_3|) 1 0)) InVars {ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [294] L3812-2-->L3772-5: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_5} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [241] L3772-5-->L3772-6: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_6 |v_ULTIMATE.start_ldv_assert_#in~expression_4|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_4|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_6} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [249] L3772-6-->L3772-9: Formula: (not (= 0 v_ULTIMATE.start_ldv_assert_~expression_8)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_8} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [233] L3772-9-->L3814: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~mem32=|v_ULTIMATE.start_my_drv_probe_#t~mem32_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~mem32] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [211] L3814-->L3814-1: Formula: (and (<= 0 (+ |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483648)) (<= |v_ULTIMATE.start_my_drv_probe_#t~nondet33_2| 2147483647)) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_2|} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [210] L3814-1-->L3814-2: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_2 |v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|) InVars {ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_3|, ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_2} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_~res~0] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [189] L3814-2-->L3815: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet33=|v_ULTIMATE.start_my_drv_probe_#t~nondet33_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet33] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [289] L3815-->L3819: Formula: (= v_ULTIMATE.start_my_drv_probe_~res~0_4 0) InVars {ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} OutVars{ULTIMATE.start_my_drv_probe_~res~0=v_ULTIMATE.start_my_drv_probe_~res~0_4} AuxVars[] AssignedVars[] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 [250] L3819-->L3822: Formula: (and (= v_~my_dev~0.base_2 v_ULTIMATE.start_my_drv_probe_~data.base_8) (= v_~my_dev~0.offset_2 (+ v_ULTIMATE.start_my_drv_probe_~data.offset_8 40))) InVars {ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_2, ULTIMATE.start_my_drv_probe_~data.base=v_ULTIMATE.start_my_drv_probe_~data.base_8, ULTIMATE.start_my_drv_probe_~data.offset=v_ULTIMATE.start_my_drv_probe_~data.offset_8, ~my_dev~0.base=v_~my_dev~0.base_2} AuxVars[] AssignedVars[~my_dev~0.base, ~my_dev~0.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [222] L3822-->L3822-1: Formula: (and (= (store |v_#memory_int_10| |v_~#t1~0.base_3| (store (select |v_#memory_int_10| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| 0)) |v_#memory_int_9|) (= |v_#memory_$Pointer$.offset_5| (store |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.offset_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.offset_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|)))) (= (store |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3| (store (select |v_#memory_$Pointer$.base_6| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3| (select (select |v_#memory_$Pointer$.base_5| |v_~#t1~0.base_3|) |v_~#t1~0.offset_3|))) |v_#memory_$Pointer$.base_5|)) InVars {#memory_int=|v_#memory_int_10|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_6|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_6|} OutVars{#memory_int=|v_#memory_int_9|, ~#t1~0.offset=|v_~#t1~0.offset_3|, ~#t1~0.base=|v_~#t1~0.base_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_5|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_5|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 [340] L3822-1-->my_callbackENTRY: Formula: (and (= 0 |v_Thread0_my_callback_#in~arg.offset_3|) (= 0 |v_Thread0_my_callback_#in~arg.base_3|) (= v_Thread0_my_callback_thidvar0_2 0)) InVars {} OutVars{Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_3|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_2, Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread0_my_callback_#in~arg.base, Thread0_my_callback_thidvar0, Thread0_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [320] my_callbackENTRY-->L3794: Formula: (and (= v_Thread0_my_callback_~arg.offset_1 |v_Thread0_my_callback_#in~arg.offset_1|) (= v_Thread0_my_callback_~arg.base_1 |v_Thread0_my_callback_#in~arg.base_1|)) InVars {Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|} OutVars{Thread0_my_callback_#in~arg.offset=|v_Thread0_my_callback_#in~arg.offset_1|, Thread0_my_callback_#in~arg.base=|v_Thread0_my_callback_#in~arg.base_1|, Thread0_my_callback_~arg.offset=v_Thread0_my_callback_~arg.offset_1, Thread0_my_callback_~arg.base=v_Thread0_my_callback_~arg.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~arg.offset, Thread0_my_callback_~arg.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [321] L3794-->L3795: Formula: true InVars {} OutVars{Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_1, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_1} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [226] L3822-2-->L3823: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet34=|v_ULTIMATE.start_my_drv_probe_#t~nondet34_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet34] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [322] L3795-->L3795-1: Formula: (and (= v_Thread0_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread0_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_1, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_1, ~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} AuxVars[] AssignedVars[Thread0_my_callback_~__mptr~0.base, Thread0_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [323] L3795-1-->L3799: Formula: (and (= v_Thread0_my_callback_~data~0.base_2 v_Thread0_my_callback_~__mptr~0.base_2) (= v_Thread0_my_callback_~data~0.offset_2 (+ v_Thread0_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2} OutVars{Thread0_my_callback_~__mptr~0.base=v_Thread0_my_callback_~__mptr~0.base_2, Thread0_my_callback_~__mptr~0.offset=v_Thread0_my_callback_~__mptr~0.offset_2, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_2, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_2} AuxVars[] AssignedVars[Thread0_my_callback_~data~0.offset, Thread0_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [324] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread0_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread0_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread0_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread0_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [325] L3799-1-->L3800: Formula: (= |v_Thread0_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread0_my_callback_~data~0.base_4) (+ v_Thread0_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} OutVars{#memory_int=|v_#memory_int_29|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_4, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_1|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_4} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [302] L3823-->L3823-1: Formula: (and (= (store |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.base_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.base_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.base_7|) (= (store |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3| (store (select |v_#memory_$Pointer$.offset_8| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| (select (select |v_#memory_$Pointer$.offset_7| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3|))) |v_#memory_$Pointer$.offset_7|) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_~#t2~0.base_3| (store (select |v_#memory_int_12| |v_~#t2~0.base_3|) |v_~#t2~0.offset_3| 1)))) InVars {#memory_int=|v_#memory_int_12|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_8|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_8|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} OutVars{#memory_int=|v_#memory_int_11|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_7|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_7|, ~#t2~0.base=|v_~#t2~0.base_3|, ~#t2~0.offset=|v_~#t2~0.offset_3|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 [341] L3823-1-->my_callbackENTRY: Formula: (and (= |v_Thread1_my_callback_#in~arg.base_3| 0) (= 0 |v_Thread1_my_callback_#in~arg.offset_3|) (= v_Thread1_my_callback_thidvar0_2 1)) InVars {} OutVars{Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_2, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_3|, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_3|} AuxVars[] AssignedVars[Thread1_my_callback_thidvar0, Thread1_my_callback_#in~arg.base, Thread1_my_callback_#in~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [292] L3823-2-->L3824: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_probe_#t~nondet35=|v_ULTIMATE.start_my_drv_probe_#t~nondet35_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#t~nondet35] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [264] L3824-->L3828: Formula: (= |v_ULTIMATE.start_my_drv_probe_#res_2| 0) InVars {} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_probe_#res] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [330] my_callbackENTRY-->L3794: Formula: (and (= v_Thread1_my_callback_~arg.offset_1 |v_Thread1_my_callback_#in~arg.offset_1|) (= v_Thread1_my_callback_~arg.base_1 |v_Thread1_my_callback_#in~arg.base_1|)) InVars {Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} OutVars{Thread1_my_callback_~arg.base=v_Thread1_my_callback_~arg.base_1, Thread1_my_callback_~arg.offset=v_Thread1_my_callback_~arg.offset_1, Thread1_my_callback_#in~arg.offset=|v_Thread1_my_callback_#in~arg.offset_1|, Thread1_my_callback_#in~arg.base=|v_Thread1_my_callback_#in~arg.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_~arg.base, Thread1_my_callback_~arg.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [331] L3794-->L3795: Formula: true InVars {} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_1, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [315] L3828-->L3851-2: Formula: (= |v_ULTIMATE.start_main_#t~ret41_2| |v_ULTIMATE.start_my_drv_probe_#res_4|) InVars {ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|} OutVars{ULTIMATE.start_my_drv_probe_#res=|v_ULTIMATE.start_my_drv_probe_#res_4|, ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [275] L3851-2-->L3851-3: Formula: (and (<= |v_ULTIMATE.start_main_#t~ret41_3| 2147483647) (<= 0 (+ |v_ULTIMATE.start_main_#t~ret41_3| 2147483648))) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_3|} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [273] L3851-3-->L3851-4: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_3 |v_ULTIMATE.start_main_#t~ret41_4|) InVars {ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_4|, ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_3} AuxVars[] AssignedVars[ULTIMATE.start_main_~probe_ret~0] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [274] L3851-4-->L3852: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~ret41=|v_ULTIMATE.start_main_#t~ret41_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ret41] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [246] L3852-->L3853: Formula: (= v_ULTIMATE.start_main_~probe_ret~0_4 0) InVars {ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} OutVars{ULTIMATE.start_main_~probe_ret~0=v_ULTIMATE.start_main_~probe_ret~0_4} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [304] L3853-->L3853-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1| |v_ULTIMATE.start_main_~#data~1.base_4|) (= |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1| |v_ULTIMATE.start_main_~#data~1.offset_4|)) InVars {ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|} OutVars{ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_4|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_1|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_1|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#in~data.offset, ULTIMATE.start_my_drv_disconnect_#in~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [310] L3853-1-->L3831: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_1|, ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_1, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_1|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_1|, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_1, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_1|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_1|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38, ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~data.base, ULTIMATE.start_my_drv_disconnect_~#status~0.base, ULTIMATE.start_my_drv_disconnect_#t~mem36, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [305] L3831-->L3832: Formula: (and (= v_ULTIMATE.start_my_drv_disconnect_~data.base_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|) (= v_ULTIMATE.start_my_drv_disconnect_~data.offset_2 |v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|)) InVars {ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|} OutVars{ULTIMATE.start_my_drv_disconnect_~data.offset=v_ULTIMATE.start_my_drv_disconnect_~data.offset_2, ULTIMATE.start_my_drv_disconnect_~data.base=v_ULTIMATE.start_my_drv_disconnect_~data.base_2, ULTIMATE.start_my_drv_disconnect_#in~data.offset=|v_ULTIMATE.start_my_drv_disconnect_#in~data.offset_2|, ULTIMATE.start_my_drv_disconnect_#in~data.base=|v_ULTIMATE.start_my_drv_disconnect_#in~data.base_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~data.offset, ULTIMATE.start_my_drv_disconnect_~data.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [266] L3832-->L3832-1: Formula: (and (= |v_#length_7| (store |v_#length_8| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 4)) (= (store |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2| 1) |v_#valid_9|) (= 0 (select |v_#valid_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|)) (= |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2| 0) (not (= 0 |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|))) InVars {#length=|v_#length_8|, #valid=|v_#valid_10|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_2|, #length=|v_#length_7|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_2|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base, #valid, #length] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [268] L3832-1-->L3833: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2| (select (select |v_#memory_int_13| |v_~#t1~0.base_4|) |v_~#t1~0.offset_4|)) InVars {#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|} OutVars{#memory_int=|v_#memory_int_13|, ~#t1~0.offset=|v_~#t1~0.offset_4|, ~#t1~0.base=|v_~#t1~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_2|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [332] L3795-->L3795-1: Formula: (and (= v_Thread1_my_callback_~__mptr~0.offset_1 v_~my_dev~0.offset_3) (= v_Thread1_my_callback_~__mptr~0.base_1 v_~my_dev~0.base_3)) InVars {~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3} OutVars{~my_dev~0.offset=v_~my_dev~0.offset_3, ~my_dev~0.base=v_~my_dev~0.base_3, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_1, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_1} AuxVars[] AssignedVars[Thread1_my_callback_~__mptr~0.base, Thread1_my_callback_~__mptr~0.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [333] L3795-1-->L3799: Formula: (and (= v_Thread1_my_callback_~data~0.base_2 v_Thread1_my_callback_~__mptr~0.base_2) (= v_Thread1_my_callback_~data~0.offset_2 (+ v_Thread1_my_callback_~__mptr~0.offset_2 (- 40)))) InVars {Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} OutVars{Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_2, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_2, Thread1_my_callback_~__mptr~0.base=v_Thread1_my_callback_~__mptr~0.base_2, Thread1_my_callback_~__mptr~0.offset=v_Thread1_my_callback_~__mptr~0.offset_2} AuxVars[] AssignedVars[Thread1_my_callback_~data~0.offset, Thread1_my_callback_~data~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [334] L3799-->L3799-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_3 40))) (and (= |v_#memory_$Pointer$.base_17| (store |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.base_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.base_17| v_Thread1_my_callback_~data~0.base_3) .cse0)))) (= (store |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_$Pointer$.offset_18| v_Thread1_my_callback_~data~0.base_3) .cse0 (select (select |v_#memory_$Pointer$.offset_17| v_Thread1_my_callback_~data~0.base_3) .cse0))) |v_#memory_$Pointer$.offset_17|) (= (store |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3 (store (select |v_#memory_int_28| v_Thread1_my_callback_~data~0.base_3) .cse0 1)) |v_#memory_int_27|))) InVars {#memory_int=|v_#memory_int_28|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_18|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_18|} OutVars{#memory_int=|v_#memory_int_27|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_3, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_17|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_3, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_17|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [335] L3799-1-->L3800: Formula: (= |v_Thread1_my_callback_#t~mem30_1| (select (select |v_#memory_int_29| v_Thread1_my_callback_~data~0.base_4) (+ v_Thread1_my_callback_~data~0.offset_4 44))) InVars {#memory_int=|v_#memory_int_29|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} OutVars{#memory_int=|v_#memory_int_29|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_1|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_4, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_4} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [336] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread1_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread1_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread1_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread1_my_callback_~data~0.base_5) .cse0 (+ |v_Thread1_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread1_my_callback_~data~0.offset=v_Thread1_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_2|, Thread1_my_callback_~data~0.base=v_Thread1_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [337] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread1_my_callback_#t~mem30=|v_Thread1_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread1_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [338] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread1_my_callback_#res.offset_1| 0) (= |v_Thread1_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_1|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_1|} AuxVars[] AssignedVars[Thread1_my_callback_#res.offset, Thread1_my_callback_#res.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 [339] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [326] L3800-->L3800-1: Formula: (let ((.cse0 (+ v_Thread0_my_callback_~data~0.offset_5 44))) (and (= |v_#memory_$Pointer$.offset_19| (store |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.offset_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.offset_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= |v_#memory_$Pointer$.base_19| (store |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_$Pointer$.base_20| v_Thread0_my_callback_~data~0.base_5) .cse0 (select (select |v_#memory_$Pointer$.base_19| v_Thread0_my_callback_~data~0.base_5) .cse0)))) (= (store |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5 (store (select |v_#memory_int_31| v_Thread0_my_callback_~data~0.base_5) .cse0 (+ |v_Thread0_my_callback_#t~mem30_2| 1))) |v_#memory_int_30|))) InVars {#memory_$Pointer$.base=|v_#memory_$Pointer$.base_20|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_31|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_20|} OutVars{#memory_$Pointer$.base=|v_#memory_$Pointer$.base_19|, Thread0_my_callback_~data~0.offset=v_Thread0_my_callback_~data~0.offset_5, #memory_int=|v_#memory_int_30|, Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_2|, Thread0_my_callback_~data~0.base=v_Thread0_my_callback_~data~0.base_5, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_19|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#t~mem30|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [327] L3800-1-->L3802: Formula: true InVars {} OutVars{Thread0_my_callback_#t~mem30=|v_Thread0_my_callback_#t~mem30_3|} AuxVars[] AssignedVars[Thread0_my_callback_#t~mem30] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [328] L3802-->my_callbackFINAL: Formula: (and (= |v_Thread0_my_callback_#res.offset_1| 0) (= |v_Thread0_my_callback_#res.base_1| 0)) InVars {} OutVars{Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_1|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_1|} AuxVars[] AssignedVars[Thread0_my_callback_#res.base, Thread0_my_callback_#res.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 [329] my_callbackFINAL-->my_callbackEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 [342] my_callbackEXIT-->L3833-1: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5| v_Thread0_my_callback_thidvar0_4) (= |v_Thread0_my_callback_#res.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|) (= |v_Thread0_my_callback_#res.base_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|)) InVars {Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_5|, Thread0_my_callback_thidvar0=v_Thread0_my_callback_thidvar0_4, Thread0_my_callback_#res.base=|v_Thread0_my_callback_#res.base_3|, ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_5|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_5|, Thread0_my_callback_#res.offset=|v_Thread0_my_callback_#res.offset_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [217] L3833-1-->L3833-2: Formula: (and (= |v_#memory_$Pointer$.offset_9| (store |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.offset_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|))) (= (store |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_$Pointer$.base_10| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|)) |v_#memory_$Pointer$.base_9|) (= (store |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3| (store (select |v_#memory_int_15| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3| (select (select |v_#memory_int_14| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|))) |v_#memory_int_14|)) InVars {ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_10|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_15|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_10|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_2|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_3|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_9|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_2|, #memory_int=|v_#memory_int_14|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_9|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [220] L3833-2-->L3833-3: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet37.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet37.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [229] L3833-3-->L3834: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem36=|v_ULTIMATE.start_my_drv_disconnect_#t~mem36_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem36] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [303] L3834-->L3834-1: Formula: (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2| (select (select |v_#memory_int_16| |v_~#t2~0.base_4|) |v_~#t2~0.offset_4|)) InVars {#memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_2|, #memory_int=|v_#memory_int_16|, ~#t2~0.base=|v_~#t2~0.base_4|, ~#t2~0.offset=|v_~#t2~0.offset_4|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 [345] my_callbackEXIT-->L3834-2: Formula: (and (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7| |v_Thread1_my_callback_#res.offset_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7| |v_Thread1_my_callback_#res.base_5|) (= |v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7| v_Thread1_my_callback_thidvar0_6)) InVars {ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_7|, Thread1_my_callback_thidvar0=v_Thread1_my_callback_thidvar0_6, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_7|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_7|, Thread1_my_callback_#res.offset=|v_Thread1_my_callback_#res.offset_5|, Thread1_my_callback_#res.base=|v_Thread1_my_callback_#res.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [293] L3834-2-->L3834-3: Formula: (and (= (store |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.base_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|)) |v_#memory_$Pointer$.base_11|) (= |v_#memory_$Pointer$.offset_11| (store |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_$Pointer$.offset_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| |v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|))) (= (store |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4| (store (select |v_#memory_int_18| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4| (select (select |v_#memory_int_17| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|) |v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|))) |v_#memory_int_17|)) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_12|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_18|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_4|, #memory_$Pointer$.base=|v_#memory_$Pointer$.base_11|, ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_4|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_2|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_2|, #memory_int=|v_#memory_int_17|, #memory_$Pointer$.offset=|v_#memory_$Pointer$.offset_11|} AuxVars[] AssignedVars[#memory_$Pointer$.base, #memory_int, #memory_$Pointer$.offset] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [295] L3834-3-->L3834-4: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~mem38=|v_ULTIMATE.start_my_drv_disconnect_#t~mem38_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~mem38] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [300] L3834-4-->L3832-2: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset_3|, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base=|v_ULTIMATE.start_my_drv_disconnect_#t~nondet39.base_3|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset, ULTIMATE.start_my_drv_disconnect_#t~nondet39.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [271] L3832-2-->L3832-3: Formula: (= (store |v_#valid_12| |v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5| 0) |v_#valid_11|) InVars {ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_12|} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [270] L3832-3-->L3831-1: Formula: true InVars {} OutVars{ULTIMATE.start_my_drv_disconnect_~#status~0.base=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.base_6|, ULTIMATE.start_my_drv_disconnect_~#status~0.offset=|v_ULTIMATE.start_my_drv_disconnect_~#status~0.offset_6|} AuxVars[] AssignedVars[ULTIMATE.start_my_drv_disconnect_~#status~0.offset, ULTIMATE.start_my_drv_disconnect_~#status~0.base] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [311] L3831-1-->L3854: Formula: (= (select (select |v_#memory_int_19| |v_ULTIMATE.start_main_~#data~1.base_5|) (+ |v_ULTIMATE.start_main_~#data~1.offset_5| 40)) |v_ULTIMATE.start_main_#t~mem42_2|) InVars {#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} OutVars{#memory_int=|v_#memory_int_19|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_5|, ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_2|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [269] L3854-->L3854-1: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_5| (ite (= |v_ULTIMATE.start_main_#t~mem42_3| 1) 1 0)) InVars {ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_3|, ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [265] L3854-1-->L3772-10: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_9} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [232] L3772-10-->L3772-11: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_10 |v_ULTIMATE.start_ldv_assert_#in~expression_6|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_6|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_10} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [238] L3772-11-->L3772-14: Formula: (not (= v_ULTIMATE.start_ldv_assert_~expression_12 0)) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_12} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [223] L3772-14-->L3855: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~mem42=|v_ULTIMATE.start_main_#t~mem42_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem42] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [236] L3855-->L3855-1: Formula: (= |v_ULTIMATE.start_main_#t~mem43_2| (select (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#data~1.base_6|) (+ |v_ULTIMATE.start_main_~#data~1.offset_6| 44))) InVars {#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} OutVars{#memory_int=|v_#memory_int_20|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_2|, ULTIMATE.start_main_~#data~1.offset=|v_ULTIMATE.start_main_~#data~1.offset_6|, ULTIMATE.start_main_~#data~1.base=|v_ULTIMATE.start_main_~#data~1.base_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~mem43] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [225] L3855-1-->L3855-2: Formula: (= |v_ULTIMATE.start_ldv_assert_#in~expression_7| (ite (= |v_ULTIMATE.start_main_#t~mem43_3| 2) 1 0)) InVars {ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_7|, ULTIMATE.start_main_#t~mem43=|v_ULTIMATE.start_main_#t~mem43_3|} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_#in~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [215] L3855-2-->L3772-15: Formula: true InVars {} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_13} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [218] L3772-15-->L3772-16: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_14 |v_ULTIMATE.start_ldv_assert_#in~expression_8|) InVars {ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|} OutVars{ULTIMATE.start_ldv_assert_#in~expression=|v_ULTIMATE.start_ldv_assert_#in~expression_8|, ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_14} AuxVars[] AssignedVars[ULTIMATE.start_ldv_assert_~expression] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [227] L3772-16-->L3772-17: Formula: (= v_ULTIMATE.start_ldv_assert_~expression_15 0) InVars {ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} OutVars{ULTIMATE.start_ldv_assert_~expression=v_ULTIMATE.start_ldv_assert_~expression_15} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 [230] L3772-17-->ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] VAL [Thread0_my_callback_thidvar0=0, Thread0_my_callback_~__mptr~0.base=63, Thread0_my_callback_~__mptr~0.offset=40, Thread0_my_callback_~arg.base=0, Thread0_my_callback_~arg.offset=0, Thread0_my_callback_~data~0.base=63, Thread0_my_callback_~data~0.offset=0, Thread1_my_callback_thidvar0=1, Thread1_my_callback_~__mptr~0.base=63, Thread1_my_callback_~__mptr~0.offset=40, Thread1_my_callback_~arg.base=0, Thread1_my_callback_~arg.offset=0, Thread1_my_callback_~data~0.base=63, Thread1_my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |Thread0_my_callback_#in~arg.base|=0, |Thread0_my_callback_#in~arg.offset|=0, |Thread0_my_callback_#res.base|=0, |Thread0_my_callback_#res.offset|=0, |Thread1_my_callback_#in~arg.base|=0, |Thread1_my_callback_#in~arg.offset|=0, |Thread1_my_callback_#res.base|=0, |Thread1_my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 #valid := #valid[0 := 0]; VAL [|#NULL.base|=0, |#NULL.offset|=0] [?] -1 SUMMARY for call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); srcloc: L3774 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3774-1 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0] [?] -1 SUMMARY for call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); srcloc: L3774-2 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 SUMMARY for call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3774-3 VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_init_#res := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_#t~ret40 := my_drv_init_#res; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [|#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 main_~ret~0 := main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_#t~ret40|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume 0 == main_~ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_~probe_ret~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); srcloc: L3850 VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#res; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [ULTIMATE.start_main_~ret~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3809 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3809-1 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); srcloc: L3810 VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem31|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem31; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 SUMMARY for call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); srcloc: L3812 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc ldv_assert_~expression; VAL [ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 == ldv_assert_~expression); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~mem32|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~mem32; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#t~nondet33|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc my_drv_probe_#t~nondet33; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 assume !(0 != my_drv_probe_~res~0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3822 VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 0 my_callback(0, 0); VAL [ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet34; VAL [my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3823 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] FORK -1 fork 1 my_callback(0, 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_probe_#t~nondet35; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_probe_#res := 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc ~data~0.base, ~data~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_#t~ret41 := my_drv_probe_#res; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 main_~probe_ret~0 := main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~ret41|=0, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~ret41; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == main_~probe_ret~0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); srcloc: L3832 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); srcloc: L3832-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); srcloc: L3799 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3799-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 1 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 SUMMARY for call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); srcloc: L3800 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |my_callback_#t~mem30|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 havoc #t~mem30; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 #res.base, #res.offset := 0, 0; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] 0 assume true; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3833-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet37.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem36|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem36; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); srcloc: L3834 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); srcloc: L3834-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~mem38|=1, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~mem38; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.base|=0, |ULTIMATE.start_my_drv_disconnect_#t~nondet39.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); srcloc: L3832-2 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_disconnect_~#status~0.base|=50, |ULTIMATE.start_my_drv_disconnect_~#status~0.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); srcloc: L3831-1 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !(0 == ldv_assert_~expression); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem42|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc main_#t~mem42; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 SUMMARY for call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); srcloc: L3855 VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=1, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=1, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 havoc ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume 0 == ldv_assert_~expression; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 assume !false; VAL [my_callback_~__mptr~0.base=63, my_callback_~__mptr~0.offset=40, my_callback_~arg.base=0, my_callback_~arg.offset=0, my_callback_~data~0.base=63, my_callback_~data~0.offset=0, ULTIMATE.start_ldv_assert_~expression=0, ULTIMATE.start_main_~probe_ret~0=0, ULTIMATE.start_main_~ret~0=0, ULTIMATE.start_my_drv_disconnect_~data.base=63, ULTIMATE.start_my_drv_disconnect_~data.offset=0, ULTIMATE.start_my_drv_probe_~data.base=63, ULTIMATE.start_my_drv_probe_~data.offset=0, ULTIMATE.start_my_drv_probe_~res~0=0, |#NULL.base|=0, |#NULL.offset|=0, |my_callback_#in~arg.base|=0, |my_callback_#in~arg.offset|=0, |my_callback_#res.base|=0, |my_callback_#res.offset|=0, |ULTIMATE.start_ldv_assert_#in~expression|=0, |ULTIMATE.start_main_#t~mem43|=1, |ULTIMATE.start_main_~#data~1.base|=63, |ULTIMATE.start_main_~#data~1.offset|=0, |ULTIMATE.start_my_drv_disconnect_#in~data.base|=63, |ULTIMATE.start_my_drv_disconnect_#in~data.offset|=0, |ULTIMATE.start_my_drv_init_#res|=0, |ULTIMATE.start_my_drv_probe_#in~data.base|=63, |ULTIMATE.start_my_drv_probe_#in~data.offset|=0, |ULTIMATE.start_my_drv_probe_#res|=0, |~#t1~0.base|=69, |~#t1~0.offset|=0, |~#t2~0.base|=60, |~#t2~0.offset|=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] -1 #NULL.base, #NULL.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0] [?] -1 #valid := #valid[0 := 0]; VAL [#NULL.base=0, #NULL.offset=0] [L3774] -1 call ~#t1~0.base, ~#t1~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call write~init~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0] [L3774] -1 call ~#t2~0.base, ~#t2~0.offset := #Ultimate.alloc(4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3774] -1 call write~init~int(0, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0] [L3791] -1 ~my_dev~0.base, ~my_dev~0.offset := 0, 0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1.base, main_~#data~1.offset, main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL.base=0, #NULL.offset=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3848-L3862] -1 assume 0 == main_~ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL.base=0, #NULL.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3850] -1 call main_~#data~1.base, main_~#data~1.offset := #Ultimate.alloc(48); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data.base, my_drv_probe_~data.offset, my_drv_probe_~res~0; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3805-L3829] -1 my_drv_probe_~data.base, my_drv_probe_~data.offset := my_drv_probe_#in~data.base, my_drv_probe_#in~data.offset; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3808] -1 #pthreadsMutex := #pthreadsMutex[my_drv_probe_~data.base,my_drv_probe_~data.offset := 0]; VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3809] -1 call write~int(0, my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3810] -1 call write~int(0, my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 call my_drv_probe_#t~mem31 := read~int(my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 call my_drv_probe_#t~mem32 := read~int(my_drv_probe_~data.base, 44 + my_drv_probe_~data.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3815-L3816] -1 assume !(0 != my_drv_probe_~res~0); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=0, ~my_dev~0.offset=0] [L3819] -1 ~my_dev~0.base, ~my_dev~0.offset := my_drv_probe_~data.base, 40 + my_drv_probe_~data.offset; VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 call write~int(0, ~#t1~0.base, ~#t1~0.offset, 4); VAL [#NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] FORK -1 fork 0 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 0 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 0 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 0 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 call write~int(1, ~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] FORK -1 fork 1 my_callback(0, 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ~arg.base, ~arg.offset := #in~arg.base, #in~arg.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3794] 1 havoc ~data~0.base, ~data~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3852-L3856] -1 assume 0 == main_~probe_ret~0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset := main_~#data~1.base, main_~#data~1.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3831-L3836] -1 my_drv_disconnect_~data.base, my_drv_disconnect_~data.offset := my_drv_disconnect_#in~data.base, my_drv_disconnect_#in~data.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset := #Ultimate.alloc(4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0.base, ~#t1~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~__mptr~0.base, ~__mptr~0.offset := ~my_dev~0.base, ~my_dev~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3795] 1 ~data~0.base, ~data~0.offset := ~__mptr~0.base, ~__mptr~0.offset - 40; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3799] 1 call write~int(1, ~data~0.base, 40 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call #t~mem30 := read~int(~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 1 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 1 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 call write~int(1 + #t~mem30, ~data~0.base, 44 + ~data~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3802] 0 #res.base, #res.offset := 0, 0; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3793-L3803] 0 ensures true; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37.base=0, my_drv_disconnect_#t~nondet37.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37.base, my_drv_disconnect_#t~nondet37.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0.base, ~#t2~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset, my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_#t~nondet39.base=0, my_drv_disconnect_#t~nondet39.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39.base, my_drv_disconnect_#t~nondet39.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~#status~0.base=50, my_drv_disconnect_~#status~0.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0.base, my_drv_disconnect_~#status~0.offset; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 call main_#t~mem42 := read~int(main_~#data~1.base, 40 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume !(0 == ldv_assert_~expression); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 call main_#t~mem43 := read~int(main_~#data~1.base, 44 + main_~#data~1.offset, 4); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assume 0 == ldv_assert_~expression; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [L3772] -1 assert false; VAL [#in~arg.base=0, #in~arg.offset=0, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1.base=63, main_~#data~1.offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data.base=63, my_drv_disconnect_#in~data.offset=0, my_drv_disconnect_~data.base=63, my_drv_disconnect_~data.offset=0, my_drv_init_#res=0, my_drv_probe_#in~data.base=63, my_drv_probe_#in~data.offset=0, my_drv_probe_#res=0, my_drv_probe_~data.base=63, my_drv_probe_~data.offset=0, my_drv_probe_~res~0=0, ~#t1~0.base=69, ~#t1~0.offset=0, ~#t2~0.base=60, ~#t2~0.offset=0, ~__mptr~0.base=63, ~__mptr~0.offset=40, ~arg.base=0, ~arg.offset=0, ~data~0.base=63, ~data~0.offset=0, ~my_dev~0.base=63, ~my_dev~0.offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [?] -1 havoc main_#t~ret40, main_#t~ret41, main_#t~mem42, main_#t~mem43, main_#t~mem44, main_#t~mem45, main_~probe_ret~0, main_~#data~1, main_~ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 my_drv_init_#res := 0; VAL [#NULL!base=0, #NULL!offset=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_#t~ret40 := my_drv_init_#res; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= main_#t~ret40 && main_#t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 main_~ret~0 := main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_#t~ret40=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc main_#t~ret40; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == main_~ret~0 VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc main_~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call main_~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 my_drv_probe_#in~data := main_~#data~1; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#res; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3851] -1 havoc my_drv_probe_#t~mem31, my_drv_probe_#t~mem32, my_drv_probe_#t~nondet33, my_drv_probe_#t~nondet34, my_drv_probe_#t~nondet35, my_drv_probe_~data, my_drv_probe_~res~0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 my_drv_probe_~data := my_drv_probe_#in~data; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: my_drv_probe_~data!base, offset: my_drv_probe_~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call my_drv_probe_#t~mem31 := read~int({ base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem31 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem31=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc my_drv_probe_#t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call my_drv_probe_#t~mem32 := read~int({ base: my_drv_probe_~data!base, offset: 44 + my_drv_probe_~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 ldv_assert_#in~expression := (if 0 == my_drv_probe_#t~mem32 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc ldv_assert_~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~mem32=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc my_drv_probe_#t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= my_drv_probe_#t~nondet33 && my_drv_probe_#t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 my_drv_probe_~res~0 := my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#t~nondet33=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc my_drv_probe_#t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != my_drv_probe_~res~0) VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: my_drv_probe_~data!base, offset: 40 + my_drv_probe_~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc my_drv_probe_#t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc my_drv_probe_#t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 my_drv_probe_#res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_#t~ret41 := my_drv_probe_#res; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= main_#t~ret41 && main_#t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 main_~probe_ret~0 := main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~ret41=0, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc main_#t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == main_~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 my_drv_disconnect_#in~data := main_~#data~1; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3853] -1 havoc my_drv_disconnect_#t~mem36, my_drv_disconnect_#t~nondet37, my_drv_disconnect_#t~mem38, my_drv_disconnect_#t~nondet39, my_drv_disconnect_~data, my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 my_drv_disconnect_~data := my_drv_disconnect_#in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call my_drv_disconnect_~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call my_drv_disconnect_#t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join my_drv_disconnect_#t~mem36 assign my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet37, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_#t~nondet37!base=0, my_drv_disconnect_#t~nondet37!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem36=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc my_drv_disconnect_#t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call my_drv_disconnect_#t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join my_drv_disconnect_#t~mem38 assign my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(my_drv_disconnect_#t~nondet39, my_drv_disconnect_~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~mem38=1, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_#t~nondet39!base=0, my_drv_disconnect_#t~nondet39!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc my_drv_disconnect_#t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(my_drv_disconnect_~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~#status~0!base=50, my_drv_disconnect_~#status~0!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc my_drv_disconnect_~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call main_#t~mem42 := read~int({ base: main_~#data~1!base, offset: 40 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 ldv_assert_#in~expression := (if 1 == main_#t~mem42 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ldv_assert_~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem42=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc main_#t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call main_#t~mem43 := read~int({ base: main_~#data~1!base, offset: 44 + main_~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=1, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 ldv_assert_#in~expression := (if 2 == main_#t~mem43 then 1 else 0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=1, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] -1 havoc ldv_assert_~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ldv_assert_~expression := ldv_assert_#in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ldv_assert_~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ldv_assert_#in~expression=0, ldv_assert_~expression=0, main_#t~mem43=1, main_~#data~1!base=63, main_~#data~1!offset=0, main_~probe_ret~0=0, main_~ret~0=0, my_drv_disconnect_#in~data!base=63, my_drv_disconnect_#in~data!offset=0, my_drv_disconnect_~data!base=63, my_drv_disconnect_~data!offset=0, my_drv_init_#res=0, my_drv_probe_#in~data!base=63, my_drv_probe_#in~data!offset=0, my_drv_probe_#res=0, my_drv_probe_~data!base=63, my_drv_probe_~data!offset=0, my_drv_probe_~res~0=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] -1 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [?] -1 #valid[0] := 0; VAL [#NULL!base=0, #NULL!offset=0] [L3774] FCALL -1 call ~#t1~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0] [L3774] FCALL -1 call ~#t2~0 := #Ultimate.alloc(4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3774] FCALL -1 call write~init~int(0, ~#t2~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0] [L3791] -1 ~my_dev~0 := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3839] -1 #res := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 assume -2147483648 <= #t~ret40 && #t~ret40 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 ~ret~0 := #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3847] -1 havoc #t~ret40; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3848] COND TRUE -1 0 == ~ret~0 VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3849] -1 havoc ~probe_ret~0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3850] FCALL -1 call ~#data~1 := #Ultimate.alloc(48); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3805-L3829] -1 ~data := #in~data; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3808] -1 #pthreadsMutex[{ base: ~data!base, offset: ~data!offset }] := 0; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3809] FCALL -1 call write~int(0, { base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3810] FCALL -1 call write~int(0, { base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] FCALL -1 call #t~mem31 := read~int({ base: ~data!base, offset: 40 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3811] -1 havoc #t~mem31; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] FCALL -1 call #t~mem32 := read~int({ base: ~data!base, offset: 44 + ~data!offset }, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] -1 ~expression := #in~expression; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3812] -1 havoc #t~mem32; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 assume -2147483648 <= #t~nondet33 && #t~nondet33 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 ~res~0 := #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3814] -1 havoc #t~nondet33; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3815-L3816] COND FALSE -1 !(0 != ~res~0) VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=0, ~my_dev~0!offset=0] [L3819] -1 ~my_dev~0 := { base: ~data!base, offset: 40 + ~data!offset }; VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FCALL -1 call write~int(0, ~#t1~0, 4); VAL [#NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] FORK -1 fork 0 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 0 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 0 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3822] -1 havoc #t~nondet34; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 0 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 0 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FCALL -1 call write~int(1, ~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] FORK -1 fork 1 my_callback({ base: 0, offset: 0 }); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3823] -1 havoc #t~nondet35; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3824] -1 #res := 0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3793-L3803] 1 ~arg := #in~arg; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3794] 1 havoc ~data~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 assume -2147483648 <= #t~ret41 && #t~ret41 <= 2147483647; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 ~probe_ret~0 := #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3851] -1 havoc #t~ret41; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3852] COND TRUE -1 0 == ~probe_ret~0 VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3831-L3836] -1 ~data := #in~data; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ~#status~0 := #Ultimate.alloc(4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call #t~mem36 := read~int(~#t1~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~__mptr~0 := ~my_dev~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3795] 1 ~data~0 := { base: ~__mptr~0!base, offset: ~__mptr~0!offset - 40 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3799] FCALL 1 call write~int(1, { base: ~data~0!base, offset: 40 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call #t~mem30 := read~int({ base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 1 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 1 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 1 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] FCALL 0 call write~int(1 + #t~mem30, { base: ~data~0!base, offset: 44 + ~data~0!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~mem30=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3800] 0 havoc #t~mem30; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3802] 0 #res := { base: 0, offset: 0 }; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] JOIN 0 join #t~mem36 assign #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] FCALL -1 call write~$Pointer$(#t~nondet37, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~nondet37; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3833] -1 havoc #t~mem36; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call #t~mem38 := read~int(~#t2~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] JOIN 1 join #t~mem38 assign #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] FCALL -1 call write~$Pointer$(#t~nondet39, ~#status~0, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~mem38; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3834] -1 havoc #t~nondet39; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] FCALL -1 call ULTIMATE.dealloc(~#status~0); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3832] -1 havoc ~#status~0; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] FCALL -1 call #t~mem42 := read~int({ base: ~#data~1!base, offset: 40 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND FALSE -1 !(0 == ~expression) VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3854] -1 havoc #t~mem42; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3855] FCALL -1 call #t~mem43 := read~int({ base: ~#data~1!base, offset: 44 + ~#data~1!offset }, 4); VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 ~expression := #in~expression; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] COND TRUE -1 0 == ~expression VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3772] -1 assert false; VAL [#in~arg!base=0, #in~arg!offset=0, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, ~#t1~0!base=69, ~#t1~0!offset=0, ~#t2~0!base=60, ~#t2~0!offset=0, ~__mptr~0!base=63, ~__mptr~0!offset=40, ~arg!base=0, ~arg!offset=0, ~data~0!base=63, ~data~0!offset=0, ~my_dev~0!base=63, ~my_dev~0!offset=40] [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={60:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={63:40}, t1={69:0}, t2={60:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3824] -1 return 0; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 1 struct my_data *data; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3832] -1 void *status; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] -1 \read(t1) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] ----- [2018-11-23 07:26:24,139 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_e598b9fe-cb1e-4e9a-9c0c-3461993b4d9b/bin-2019/utaipan/witness.graphml [2018-11-23 07:26:24,139 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 07:26:24,140 INFO L168 Benchmark]: Toolchain (without parser) took 232570.33 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 238.6 MB). Free memory was 956.6 MB in the beginning and 1.0 GB in the end (delta: -76.3 MB). Peak memory consumption was 162.3 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,140 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 07:26:24,140 INFO L168 Benchmark]: CACSL2BoogieTranslator took 873.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.0 MB). Free memory was 956.6 MB in the beginning and 1.0 GB in the end (delta: -71.6 MB). Peak memory consumption was 95.8 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,192 INFO L168 Benchmark]: Boogie Procedure Inliner took 48.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,193 INFO L168 Benchmark]: Boogie Preprocessor took 29.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,193 INFO L168 Benchmark]: RCFGBuilder took 521.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 974.0 MB in the end (delta: 46.0 MB). Peak memory consumption was 46.0 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,193 INFO L168 Benchmark]: TraceAbstraction took 226696.34 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 86.5 MB). Free memory was 974.0 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 238.1 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,193 INFO L168 Benchmark]: Witness Printer took 4397.30 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 92.2 MB). Peak memory consumption was 92.2 MB. Max. memory is 11.5 GB. [2018-11-23 07:26:24,193 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 873.39 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.0 MB). Free memory was 956.6 MB in the beginning and 1.0 GB in the end (delta: -71.6 MB). Peak memory consumption was 95.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 48.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 29.82 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 521.95 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 974.0 MB in the end (delta: 46.0 MB). Peak memory consumption was 46.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 226696.34 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 86.5 MB). Free memory was 974.0 MB in the beginning and 1.1 GB in the end (delta: -151.0 MB). Peak memory consumption was 238.1 MB. Max. memory is 11.5 GB. * Witness Printer took 4397.30 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 92.2 MB). Peak memory consumption was 92.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 3772]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L3774] -1 pthread_t t1,t2; VAL [t1={69:0}, t2={60:0}] [L3791] -1 struct device *my_dev; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3839] -1 return 0; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3847] -1 int ret = my_drv_init(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3848] COND TRUE -1 ret==0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3849] -1 int probe_ret; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3850] -1 struct my_data data; VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3809] -1 data->shared.a = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3810] -1 data->shared.b = 0 VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3811] -1 data->shared.a VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3812] -1 data->shared.b VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3814] -1 int res = __VERIFIER_nondet_int(); VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3815] COND FALSE -1 !(\read(res)) VAL [my_dev={0:0}, t1={69:0}, t2={60:0}] [L3819] -1 my_dev = &data->dev VAL [my_dev={63:40}, t1={69:0}, t2={60:0}] [L3822] FCALL, FORK -1 pthread_create(&t1, ((void *)0), my_callback, ((void *)0)) VAL [arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 0 struct my_data *data; VAL [arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 0 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 0 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3823] FCALL, FORK -1 pthread_create(&t2, ((void *)0), my_callback, ((void *)0)) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3824] -1 return 0; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3794] 1 struct my_data *data; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3851] -1 probe_ret = my_drv_probe(&data) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3852] COND TRUE -1 probe_ret==0 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3832] -1 void *status; VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] -1 \read(t1) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3795] 1 data = ({ const typeof( ((struct my_data *)0)->dev ) *__mptr = (my_dev); (struct my_data *)( (char *)__mptr - ((unsigned long) &((struct my_data *)0)->dev) );}) VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3799] 1 data->shared.a = 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] EXPR 1 data->shared.b VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 1 data->shared.b = data->shared.b + 1 VAL [__mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 1 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3800] 0 data->shared.b = data->shared.b + 1 VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, data->shared.b=0, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3802] 0 return 0; VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3833] FCALL, JOIN 0 pthread_join(t1, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] -1 \read(t2) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3834] FCALL, JOIN 1 pthread_join(t2, &status) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3854] -1 data.shared.a VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND FALSE -1 !(!expression) VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3855] -1 data.shared.b VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] COND TRUE -1 !expression VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] [L3772] -1 __VERIFIER_error() VAL [\result={0:0}, __mptr={63:40}, arg={0:0}, arg={0:0}, data={63:0}, my_dev={63:40}, t1={69:0}, t2={60:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 148 locations, 6 error locations. UNSAFE Result, 226.5s OverallTime, 48 OverallIterations, 1 TraceHistogramMax, 174.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 8376 SDtfs, 38027 SDslu, 69674 SDs, 0 SdLazy, 41151 SolverSat, 4466 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 40.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2166 GetRequests, 114 SyntacticMatches, 71 SemanticMatches, 1981 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15425 ImplicationChecksByTransitivity, 171.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=5125occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 47 MinimizatonAttempts, 62526 StatesRemovedByMinimization, 46 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 46.0s InterpolantComputationTime, 4439 NumberOfCodeBlocks, 4439 NumberOfCodeBlocksAsserted, 48 NumberOfCheckSat, 4290 ConstructedInterpolants, 0 QuantifiedInterpolants, 6798490 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 47 InterpolantComputations, 47 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...